USHR
Unsigned shift right (immediate)
This instruction reads
each vector element in the source SIMD&FP register,
right shifts each result by an immediate value,
writes the final result to a vector,
and writes the
vector to the destination SIMD&FP register.
All the values in this instruction are unsigned integer values.
The results are truncated. For rounded results, see
URSHR.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
It has encodings from 2 classes:
Scalar
and
Vector
0
1
1
1
1
1
1
1
0
1
x
x
x
0
0
0
0
0
1
USHR D<d>, D<n>, #<shift>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if immh[3] != '1' then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let esize : integer{} = 8 << 3;
let datasize : integer{} = esize;
let elements : integer = 1;
let shift : integer = (esize * 2) - UInt(immh::immb);
let unsigned : boolean = TRUE;
let round : boolean = FALSE;
0
1
0
1
1
1
1
0
!= 0000
0
0
0
0
0
1
USHR <Vd>.<T>, <Vn>.<T>, #<shift>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if immh[3]::Q == '10' then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let esize : integer{} = 8 << HighestSetBitNZ(immh);
let datasize : integer{} = 64 << UInt(Q);
let elements : integer = datasize DIV esize;
let shift : integer = (esize * 2) - UInt(immh::immb);
let unsigned : boolean = TRUE;
let round : boolean = FALSE;
<d>
Is the number of the SIMD&FP destination register, encoded in the "Rd" field.
<n>
Is the number of the SIMD&FP source register, encoded in the "Rn" field.
<shift>
For the "Scalar" variant: is the right shift amount, in the range 1 to 64, encoded as 128 - UInt("immh:immb").
<shift>
For the "Vector" variant: is the right shift amount, in the range 1 to the element width in bits,
immh
<shift>
0001
16 - UInt(immh :: immb)
001x
32 - UInt(immh :: immb)
01xx
64 - UInt(immh :: immb)
1xxx
128 - UInt(immh :: immb)
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
Is an arrangement specifier,
immh
Q
<T>
0001
0
8B
0001
1
16B
001x
0
4H
001x
1
8H
01xx
0
2S
01xx
1
4S
1xxx
0
RESERVED
1xxx
1
2D
<Vn>
Is the name of the SIMD&FP source register, encoded in the "Rn" field.
AArch64_CheckFPAdvSIMDEnabled();
let operand : bits(datasize) = V{}(n);
var result : bits(datasize);
var element : integer;
for e = 0 to elements-1 do
let opelt : bits(esize) = operand[e*:esize];
if unsigned then
element = RShr(UInt(opelt), shift, round);
else
element = RShr(SInt(opelt), shift, round);
end;
result[e*:esize] = element[esize-1:0];
end;
V{datasize}(d) = result;
2026-03-12 12:23:09
2025-09_rel_asl1