This is a collection of Intel®’ IA32® Software Developer's Manuals (URL of the day) and AMD' AMD64 Architecture Programmer's Manual together with the related specifications, application notes, white papers, and change logs. The collection aims to keep all available revisions. It was originally created by Michal Necasek, see OS/2 Museum.

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LD64B

Single-copy atomic 64-byte Load

This instruction derives an address from a base register value, loads eight 64-bit doublewords from a memory location, and writes them to consecutive registers. The load starts at register Xt, with the data being read as X(t+7)::X(t+6)::X(t+5)::X(t+4)::X(t+3)::X(t+2)::X(t+1)::Xt = Data[511:0]. The data is loaded atomically and is required to be 64-byte aligned.

It is IMPLEMENTATION DEFINED which memory locations support this instruction. A memory location that supports LD64B also supports ST64B.

For more information, including about the memory types accessible and how the accesses are performed, see Single-copy atomic 64-byte load/store.

Integer
(FEAT_LS64)

Decode for this encoding

if !IsFeatureImplemented(FEAT_LS64) then EndOfDecode(Decode_UNDEF); end; if Rt[4:3] == '11' || Rt[0] == '1' then EndOfDecode(Decode_UNDEF); end; let withstatus : boolean = FALSE; let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let tagchecked : boolean = n != 31;

Assembler Symbols