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STGP -- A64

STGP

Store Allocation Tag and pair of registers

This instruction stores an Allocation Tag and two 64-bit doublewords to memory, from two registers. The address used for the store is calculated from the base register and an immediate signed offset scaled by the Tag Granule. The Allocation Tag is calculated from the Logical Address Tag in the base register.

This instruction generates an Unchecked access.

It has encodings from 3 classes: Post-index , Pre-index and Signed offset

Post-index
(FEAT_MTE)

313029282726252423222120191817161514131211109876543210
0110100010simm7Rt2RnRt
opcVRL

Encoding

STGP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>

Decode for this encoding

if !IsFeatureImplemented(FEAT_MTE) then EndOfDecode(Decode_UNDEF); end; let t : integer{} = UInt(Rt); let t2 : integer{} = UInt(Rt2); let n : integer{} = UInt(Rn); let offset : bits(64) = LSL(SignExtend{64}(simm7), LOG2_TAG_GRANULE); let writeback : boolean = TRUE; let postindex : boolean = TRUE;

Pre-index
(FEAT_MTE)

313029282726252423222120191817161514131211109876543210
0110100110simm7Rt2RnRt
opcVRL

Encoding

STGP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!

Decode for this encoding

if !IsFeatureImplemented(FEAT_MTE) then EndOfDecode(Decode_UNDEF); end; let t : integer{} = UInt(Rt); let t2 : integer{} = UInt(Rt2); let n : integer{} = UInt(Rn); let offset : bits(64) = LSL(SignExtend{64}(simm7), LOG2_TAG_GRANULE); let writeback : boolean = TRUE; let postindex : boolean = FALSE;

Signed offset
(FEAT_MTE)

313029282726252423222120191817161514131211109876543210
0110100100simm7Rt2RnRt
opcVRL

Encoding

STGP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]

Decode for this encoding

if !IsFeatureImplemented(FEAT_MTE) then EndOfDecode(Decode_UNDEF); end; let t : integer{} = UInt(Rt); let t2 : integer{} = UInt(Rt2); let n : integer{} = UInt(Rn); let offset : bits(64) = LSL(SignExtend{64}(simm7), LOG2_TAG_GRANULE); let writeback : boolean = FALSE; let postindex : boolean = FALSE;

Assembler Symbols

<Xt1>

Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.

<Xt2>

Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<imm>

For the "Post-index" and "Pre-index" variants: is the signed immediate offset, a multiple of 16 in the range -1024 to 1008, encoded in the "simm7" field.

For the "Signed offset" variant: is the optional signed immediate offset, a multiple of 16 in the range -1024 to 1008, defaulting to 0 and encoded in the "simm7" field.


2025-09_rel_asl1 2026-03-12 12:57:38

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