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STLURH -- A64

STLURH

Store-release register halfword (unscaled)

This instruction calculates an address from a base register value and an immediate offset, and stores a halfword to the calculated address, from a 32-bit register.

The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release

For information about addressing modes, see Load/Store addressing modes.

Unscaled offset
(FEAT_LRCPC2)

313029282726252423222120191817161514131211109876543210
01011001000imm900RnRt
sizeopc

Encoding

STLURH <Wt>, [<Xn|SP>{, #<simm>}]

Decode for this encoding

if !IsFeatureImplemented(FEAT_LRCPC2) then EndOfDecode(Decode_UNDEF); end; let offset : bits(64) = SignExtend{}(imm9); let n : integer = UInt(Rn); let t : integer = UInt(Rt); let datasize : integer{} = 16; let acquire : boolean = FALSE; let tagchecked : boolean = n != 31;

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<simm>

Is the optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field.

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2025-09_rel_asl1 2026-03-12 12:57:38

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