BFMMLA (widening) BFloat16 matrix multiply-accumulate to single-precision This instruction multiplies the 2x4 matrix of BFloat16 values held in the first source vector by the 4x2 matrix of BFloat16 values in the second source vector. If FEAT_EBF16 is not implemented or FPCR.EBF is 0, this instruction: Calculates the intermediate single-precision results as a sum of two unfused sum-of-products using two pairs of adjacent BFloat16 values from each of the source vectors, and then rounds the results before accumulation into the 2x2 matrix of single-precision results in the destination vector. This is equivalent to accumulating a 4-way dot product per destination element. Uses the non-IEEE 754 Round-to-Odd rounding mode, which forces bit 0 of an inexact result to 1, and rounds an overflow to an appropriately signed Infinity. Flushes denormalized inputs and results to zero, as if FPCR.{FZ, FIZ} is {1, 1}. Honors FPCR.AH when generating a default NaN result, otherwise disables alternative floating point behaviors, as if FPCR.AH is 0. If FEAT_EBF16 is implemented and FPCR.EBF is 1, this instruction: Calculates the intermediate single-precision results as a sum of two fused sum-of-products using two pairs of adjacent BFloat16 values from each of the source vectors, and then rounds the results before accumulation into the 2x2 matrix of single-precision results in the destination vector. This is equivalent to accumulating a 4-way dot product per destination element. Follows all other floating-point behaviors that apply to single-precision arithmetic, as governed by FPCR.RMode, FPCR.FZ, FPCR.AH, and FPCR.FIZ. Irrespective of FEAT_EBF16 and FPCR.EBF, this instruction: Does not modify the cumulative FPSR exception bits (IDC, IXC, UFC, OFC, DZC, and IOC). Disables trapped floating-point exceptions, as if the FPCR trap enable bits (IDE, IXE, UFE, OFE, DZE, and IOE) are all zero. Generates only the default NaN, as if FPCR.DN is 1. ID_AA64ISAR1_EL1.BF16 indicates whether this instruction is supported. Arm expects that the BFMMLA instruction will deliver a peak BFloat16 multiply throughput that is at least as high as can be achieved using two BFDOT (vector) instructions, with a goal that it should have significantly higher throughput. 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 1 BFMMLA <Vd>.4S, <Vn>.8H, <Vm>.8H if !IsFeatureImplemented(FEAT_BF16) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); <Vd> Is the name of the SIMD&FP third source and destination register, encoded in the "Rd" field. <Vn> Is the name of the first SIMD&FP source register, encoded in the "Rn" field. <Vm> Is the name of the second SIMD&FP source register, encoded in the "Rm" field. AArch64_CheckFPAdvSIMDEnabled(); let op1 : bits(128) = V{}(n); let op2 : bits(128) = V{}(m); let acc : bits(128) = V{}(d); V{128}(d) = BFMatMulAddH(acc, op1, op2, FPCR()); 2026-03-26 20:27:25 2026-03_rel