<?xml version="1.0" ?><?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?><!DOCTYPE instructionsection  PUBLIC '-//ARM//DTD instructionsection //EN'  'iform-p.dtd'><!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. --><!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. --><instructionsection id="CRC32C" title="CRC32CB, CRC32CH, CRC32CW, CRC32CX -- A64" type="instruction">
  <docvars>
    <docvar key="feature" value="crc"/>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="A64"/>
  </docvars>
  <heading>CRC32CB, CRC32CH, CRC32CW, CRC32CX</heading>
  <desc>
    <brief>
      <para>CRC32C checksum</para>
    </brief>
    <authored>
      <para>This instruction performs a cyclic redundancy check (CRC)
calculation on a value held in a general-purpose register. It takes
an input CRC value in the first source operand, performs a CRC on
the input value in the second source operand, and returns the output
CRC value. The second source operand can be 8, 16, 32, or 64
bits. To align with common usage, the bit order of the values is
reversed as part of the operation, and the polynomial
<hexnumber>0x1EDC6F41</hexnumber> is used for the CRC calculation.</para>
      <para>In an Armv8.0 implementation, this is an <arm-defined-word>OPTIONAL</arm-defined-word> instruction.
From Armv8.1, it is mandatory for all implementations to implement this instruction.</para>
      <note>
        <para><register_link id="AArch64-id_aa64isar0_el1.xml" state="AArch64">ID_AA64ISAR0_EL1</register_link>.CRC32
indicates whether this instruction is supported.</para>
      </note>
    </authored>
  </desc>
  <operationalnotes>
    <operationalnote>
      <operationalnote_content>
        <para>This instruction is a data-independent-time instruction as described in <xref linkend="ARMARM_BEICCDDAB3">About PSTATE.DIT</xref>.</para>
      </operationalnote_content>
    </operationalnote>
  </operationalnotes>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="CRC" oneof="1" id="iclass_crc" no_encodings="4" isa="A64">
      <docvars>
        <docvar key="feature" value="crc"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A64"/>
      </docvars>
      <iclassintro count="4"/>
      <arch_variants>
        <arch_variant feature="FEAT_CRC32" name="v8Ap0"/>
      </arch_variants>
      <regdiagram form="32" psname="A64.dpreg.dp_2src.CRC32CB_32C_dp_2src" tworows="1">
        <box hibit="31" width="1" name="sf" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="30" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="29" name="S" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="28" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="15" width="3" settings="3">
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="12" name="C" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="11" width="2" name="sz" usename="1">
          <c colspan="2"/>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="CRC32CB_32C_dp_2src" oneofinclass="4" oneof="4" label="CRC32CB" bitdiffs="sf == 0 &amp;&amp; sz == 00">
        <docvars>
          <docvar key="datatype" value="32"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="feature" value="crc"/>
          <docvar key="mnemonic" value="CRC32CB"/>
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>0</c>
        </box>
        <box hibit="11" width="2" name="sz">
          <c>0</c>
          <c>0</c>
        </box>
        <asmtemplate><text>CRC32CB  </text><a hover="Is the 32-bit name of the general-purpose accumulator output register, encoded in the &quot;Rd&quot; field." link="WdOrWZR__2">&lt;Wd&gt;</a><text>, </text><a hover="Is the 32-bit name of the general-purpose accumulator input register, encoded in the &quot;Rn&quot; field." link="WnOrWZR__4">&lt;Wn&gt;</a><text>, </text><a hover="Is the 32-bit name of the general-purpose data source register, encoded in the &quot;Rm&quot; field." link="WmOrWZR__5">&lt;Wm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CRC32CH_32C_dp_2src" oneofinclass="4" oneof="4" label="CRC32CH" bitdiffs="sf == 0 &amp;&amp; sz == 01">
        <docvars>
          <docvar key="datatype" value="32"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="feature" value="crc"/>
          <docvar key="mnemonic" value="CRC32CH"/>
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>0</c>
        </box>
        <box hibit="11" width="2" name="sz">
          <c>0</c>
          <c>1</c>
        </box>
        <asmtemplate><text>CRC32CH  </text><a hover="Is the 32-bit name of the general-purpose accumulator output register, encoded in the &quot;Rd&quot; field." link="WdOrWZR__2">&lt;Wd&gt;</a><text>, </text><a hover="Is the 32-bit name of the general-purpose accumulator input register, encoded in the &quot;Rn&quot; field." link="WnOrWZR__4">&lt;Wn&gt;</a><text>, </text><a hover="Is the 32-bit name of the general-purpose data source register, encoded in the &quot;Rm&quot; field." link="WmOrWZR__5">&lt;Wm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CRC32CW_32C_dp_2src" oneofinclass="4" oneof="4" label="CRC32CW" bitdiffs="sf == 0 &amp;&amp; sz == 10">
        <docvars>
          <docvar key="datatype" value="32"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="feature" value="crc"/>
          <docvar key="mnemonic" value="CRC32CW"/>
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>0</c>
        </box>
        <box hibit="11" width="2" name="sz">
          <c>1</c>
          <c>0</c>
        </box>
        <asmtemplate><text>CRC32CW  </text><a hover="Is the 32-bit name of the general-purpose accumulator output register, encoded in the &quot;Rd&quot; field." link="WdOrWZR__2">&lt;Wd&gt;</a><text>, </text><a hover="Is the 32-bit name of the general-purpose accumulator input register, encoded in the &quot;Rn&quot; field." link="WnOrWZR__4">&lt;Wn&gt;</a><text>, </text><a hover="Is the 32-bit name of the general-purpose data source register, encoded in the &quot;Rm&quot; field." link="WmOrWZR__5">&lt;Wm&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CRC32CX_64C_dp_2src" oneofinclass="4" oneof="4" label="CRC32CX" bitdiffs="sf == 1 &amp;&amp; sz == 11">
        <docvars>
          <docvar key="datatype" value="64"/>
          <docvar key="feature" value="crc"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="CRC32CX"/>
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>1</c>
        </box>
        <box hibit="11" width="2" name="sz">
          <c>1</c>
          <c>1</c>
        </box>
        <asmtemplate><text>CRC32CX  </text><a hover="Is the 32-bit name of the general-purpose accumulator output register, encoded in the &quot;Rd&quot; field." link="WdOrWZR__2">&lt;Wd&gt;</a><text>, </text><a hover="Is the 32-bit name of the general-purpose accumulator input register, encoded in the &quot;Rn&quot; field." link="WnOrWZR__4">&lt;Wn&gt;</a><text>, </text><a hover="Is the 64-bit name of the general-purpose data source register, encoded in the &quot;Rm&quot; field." link="XmOrXZR__8">&lt;Xm&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.dpreg.dp_2src.CRC32CB_32C_dp_2src" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !IsFeatureImplemented(FEAT_CRC32) then <a link="func_EndOfDecode_1" file="shared_pseudocode.xml">EndOfDecode</a>(<a link="enum_Decode_UNDEF" file="shared_pseudocode.xml">Decode_UNDEF</a>); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);
if sf == '1' &amp;&amp; sz != '11' then <a link="func_EndOfDecode_1" file="shared_pseudocode.xml">EndOfDecode</a>(<a link="enum_Decode_UNDEF" file="shared_pseudocode.xml">Decode_UNDEF</a>); end;
if sf == '0' &amp;&amp; sz == '11' then <a link="func_EndOfDecode_1" file="shared_pseudocode.xml">EndOfDecode</a>(<a link="enum_Decode_UNDEF" file="shared_pseudocode.xml">Decode_UNDEF</a>); end;
let size : integer{} = 8 &lt;&lt; UInt(sz);</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CRC32CB_32C_dp_2src, CRC32CH_32C_dp_2src, CRC32CW_32C_dp_2src, CRC32CX_64C_dp_2src" symboldefcount="1">
      <symbol link="WdOrWZR__2">&lt;Wd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 32-bit name of the general-purpose accumulator output register, encoded in the &quot;Rd&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CRC32CB_32C_dp_2src, CRC32CH_32C_dp_2src, CRC32CW_32C_dp_2src, CRC32CX_64C_dp_2src" symboldefcount="1">
      <symbol link="WnOrWZR__4">&lt;Wn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 32-bit name of the general-purpose accumulator input register, encoded in the &quot;Rn&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CRC32CB_32C_dp_2src, CRC32CH_32C_dp_2src, CRC32CW_32C_dp_2src" symboldefcount="1">
      <symbol link="WmOrWZR__5">&lt;Wm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 32-bit name of the general-purpose data source register, encoded in the &quot;Rm&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CRC32CX_64C_dp_2src" symboldefcount="1">
      <symbol link="XmOrXZR__8">&lt;Xm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 64-bit name of the general-purpose data source register, encoded in the &quot;Rm&quot; field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A64.dpreg.dp_2src.CRC32CB_32C_dp_2src" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">let acc : bits(32)     = X{}(n);     // accumulator
let val : bits(size)     = X{}(m);   // input value
let poly : bits(32)    = 0x1EDC6F41[31:0];

let tempacc : bits(32+size) = <a link="func_BitReverse_2" file="shared_pseudocode.xml">BitReverse</a>{32}(acc)::Zeros{size};
let tempval : bits(size+32) = <a link="func_BitReverse_2" file="shared_pseudocode.xml">BitReverse</a>{size}(val)::Zeros{32};

// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
<a link="accessor_X_2" file="shared_pseudocode.xml">X</a>{32}(d) = <a link="func_BitReverse_2" file="shared_pseudocode.xml">BitReverse</a>{32}(<a link="func_Poly32Mod2_3" file="shared_pseudocode.xml">Poly32Mod2</a>{32+size}(tempacc XOR tempval, poly));</pstext></ps>
  </ps_section>
  <timestamp>2026-03-26 20:27:25</timestamp>
  <commit_id>2026-03_rel</commit_id>
</instructionsection>