<?xml version="1.0" ?><?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?><!DOCTYPE instructionsection  PUBLIC '-//ARM//DTD instructionsection //EN'  'iform-p.dtd'><!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. --><!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. --><instructionsection id="CSEL" title="CSEL -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="CSEL"/>
  </docvars>
  <heading>CSEL</heading>
  <desc>
    <brief>
      <para>Conditional select</para>
    </brief>
    <authored>
      <para>This instruction writes the value of the first source register to the
destination register if the condition is TRUE. If the condition is FALSE,
it writes the value of the second source register to the destination register.</para>
    </authored>
  </desc>
  <operationalnotes>
    <operationalnote>
      <operationalnote_content>
        <para>This instruction is a data-independent-time instruction as described in <xref linkend="ARMARM_BEICCDDAB3">About PSTATE.DIT</xref>.</para>
      </operationalnote_content>
    </operationalnote>
  </operationalnotes>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="Integer" oneof="1" id="iclass_integer" no_encodings="2" isa="A64">
      <docvars>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="CSEL"/>
      </docvars>
      <iclassintro count="2"/>
      <regdiagram form="32" psname="A64.dpreg.condsel.CSEL_32_condsel" tworows="1">
        <box hibit="31" width="1" name="sf" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="30" name="op" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="29" name="S" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="28" width="8" settings="8">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="15" width="4" name="cond" usename="1">
          <c colspan="4"/>
        </box>
        <box hibit="11" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="10" name="o2" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="CSEL_32_condsel" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
        <docvars>
          <docvar key="datatype" value="32"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="CSEL"/>
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>0</c>
        </box>
        <asmtemplate><text>CSEL  </text><a hover="Is the 32-bit name of the general-purpose destination register, encoded in the &quot;Rd&quot; field." link="WdOrWZR">&lt;Wd&gt;</a><text>, </text><a hover="Is the 32-bit name of the first general-purpose source register, encoded in the &quot;Rn&quot; field." link="WnOrWZR__3">&lt;Wn&gt;</a><text>, </text><a hover="Is the 32-bit name of the second general-purpose source register, encoded in the &quot;Rm&quot; field." link="WmOrWZR__2">&lt;Wm&gt;</a><text>, </text><a hover="Is one of the standard conditions, encoded in the standard way, and " link="cond_option">&lt;cond&gt;</a></asmtemplate>
      </encoding>
      <encoding name="CSEL_64_condsel" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
        <docvars>
          <docvar key="datatype" value="64"/>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="CSEL"/>
        </docvars>
        <box hibit="31" width="1" name="sf">
          <c>1</c>
        </box>
        <asmtemplate><text>CSEL  </text><a hover="Is the 64-bit name of the general-purpose destination register, encoded in the &quot;Rd&quot; field." link="XdOrXZR__6">&lt;Xd&gt;</a><text>, </text><a hover="Is the 64-bit name of the first general-purpose source register, encoded in the &quot;Rn&quot; field." link="XnOrXZR__12">&lt;Xn&gt;</a><text>, </text><a hover="Is the 64-bit name of the second general-purpose source register, encoded in the &quot;Rm&quot; field." link="XmOrXZR__4">&lt;Xm&gt;</a><text>, </text><a hover="Is one of the standard conditions, encoded in the standard way, and " link="cond_option">&lt;cond&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.dpreg.condsel.CSEL_32_condsel" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);
let datasize : integer{} = 32 &lt;&lt; UInt(sf);
let condition : bits(4) = cond;</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="CSEL_32_condsel" symboldefcount="1">
      <symbol link="WdOrWZR">&lt;Wd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 32-bit name of the general-purpose destination register, encoded in the &quot;Rd&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CSEL_32_condsel" symboldefcount="1">
      <symbol link="WnOrWZR__3">&lt;Wn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 32-bit name of the first general-purpose source register, encoded in the &quot;Rn&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CSEL_32_condsel" symboldefcount="1">
      <symbol link="WmOrWZR__2">&lt;Wm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 32-bit name of the second general-purpose source register, encoded in the &quot;Rm&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CSEL_32_condsel, CSEL_64_condsel" symboldefcount="1">
      <symbol link="cond_option">&lt;cond&gt;</symbol>
      <definition encodedin="cond">
        <intro>Is one of the standard conditions, encoded in the standard way, and </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">cond</entry>
                <entry class="symbol">&lt;cond&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0000</entry>
                <entry class="symbol">EQ</entry>
              </row>
              <row>
                <entry class="bitfield">0001</entry>
                <entry class="symbol">NE</entry>
              </row>
              <row>
                <entry class="bitfield">0010</entry>
                <entry class="symbol">CS</entry>
              </row>
              <row>
                <entry class="bitfield">0011</entry>
                <entry class="symbol">CC</entry>
              </row>
              <row>
                <entry class="bitfield">0100</entry>
                <entry class="symbol">MI</entry>
              </row>
              <row>
                <entry class="bitfield">0101</entry>
                <entry class="symbol">PL</entry>
              </row>
              <row>
                <entry class="bitfield">0110</entry>
                <entry class="symbol">VS</entry>
              </row>
              <row>
                <entry class="bitfield">0111</entry>
                <entry class="symbol">VC</entry>
              </row>
              <row>
                <entry class="bitfield">1000</entry>
                <entry class="symbol">HI</entry>
              </row>
              <row>
                <entry class="bitfield">1001</entry>
                <entry class="symbol">LS</entry>
              </row>
              <row>
                <entry class="bitfield">1010</entry>
                <entry class="symbol">GE</entry>
              </row>
              <row>
                <entry class="bitfield">1011</entry>
                <entry class="symbol">LT</entry>
              </row>
              <row>
                <entry class="bitfield">1100</entry>
                <entry class="symbol">GT</entry>
              </row>
              <row>
                <entry class="bitfield">1101</entry>
                <entry class="symbol">LE</entry>
              </row>
              <row>
                <entry class="bitfield">1110</entry>
                <entry class="symbol">AL</entry>
              </row>
              <row>
                <entry class="bitfield">1111</entry>
                <entry class="symbol">NV</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="CSEL_64_condsel" symboldefcount="1">
      <symbol link="XdOrXZR__6">&lt;Xd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the 64-bit name of the general-purpose destination register, encoded in the &quot;Rd&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CSEL_64_condsel" symboldefcount="1">
      <symbol link="XnOrXZR__12">&lt;Xn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the first general-purpose source register, encoded in the &quot;Rn&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="CSEL_64_condsel" symboldefcount="1">
      <symbol link="XmOrXZR__4">&lt;Xm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the 64-bit name of the second general-purpose source register, encoded in the &quot;Rm&quot; field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A64.dpreg.condsel.CSEL_32_condsel" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">var result : bits(datasize);
if <a link="func_ConditionHolds_1" file="shared_pseudocode.xml">ConditionHolds</a>(condition) then
    result = <a link="accessor_X_2" file="shared_pseudocode.xml">X</a>{datasize}(n);
else
    result = <a link="accessor_X_2" file="shared_pseudocode.xml">X</a>{datasize}(m);
end;

<a link="accessor_X_2" file="shared_pseudocode.xml">X</a>{datasize}(d) = result;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-26 20:27:25</timestamp>
  <commit_id>2026-03_rel</commit_id>
</instructionsection>