ESB
Error synchronization barrier
This instruction is an error synchronization event that might also update DISR_EL1 and VDISR_EL2.
This instruction can be used at all Exception levels and in Debug state.
In Debug state, this instruction behaves as if SError interrupts are masked at all Exception levels.
For more information, see RAS PE architecture
and Arm® Reliability, Availability, and Serviceability (RAS) System Architecture, for A-profile architecture (ARM IHI 0100).
If FEAT_RAS is not implemented, this instruction executes as a NOP.
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ESB
if !IsFeatureImplemented(FEAT_RAS) then EndOfDecode(Decode_NOP); end;
SynchronizeErrors();
AArch64_ESBOperation();
if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then
AArch64_vESBOperation();
elsif IsFeatureImplemented(FEAT_E3DSE) && PSTATE.EL != EL3 then
AArch64_dESBOperation();
end;
TakeUnmaskedSErrorInterrupts();
2026-03-26 20:27:25
2026-03_rel