FCCMP Floating-point conditional quiet compare (scalar) This instruction compares the two SIMD&FP source register values and writes the result to the PSTATE.{N, Z, C, V} flags. If the condition does not pass, then the PSTATE.{N, Z, C, V} flags are set to the flag bit specifier. This instruction raises an Invalid Operation floating-point exception if either or both of the operands is a signaling NaN. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. The IEEE 754 standard specifies that the result of a comparison is precisely one of <, ==, > or unordered. If either or both of the operands is a NaN, they are unordered, and all three of (Operand1 < Operand2), (Operand1 == Operand2) and (Operand1 > Operand2) are false. An unordered comparison sets the PSTATE condition flags to N=0, Z=0, C=1, and V=1. If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the NZCV condition flags written by this instruction might be significantly delayed. 0 0 0 1 1 1 1 0 1 0 1 0 1 1 FCCMP <Hn>, <Hm>, #<nzcv>, <cond> 0 0 FCCMP <Sn>, <Sm>, #<nzcv>, <cond> 0 1 FCCMP <Dn>, <Dm>, #<nzcv>, <cond> if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; if ftype == '10' then EndOfDecode(Decode_UNDEF); end; if ftype == '11' && !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); end; let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let datasize : integer{} = 8 << UInt(ftype XOR '10'); let condition : bits(4) = cond; var flags : bits(4) = nzcv; <Hn> Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field. <Hm> Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field. <nzcv> Is the flag bit specifier, an immediate in the range 0 to 15, giving the alternative state for the 4-bit NZCV condition flags, encoded in the "nzcv" field. <cond> Is one of the standard conditions, encoded in the standard way, and cond <cond> 0000 EQ 0001 NE 0010 CS 0011 CC 0100 MI 0101 PL 0110 VS 0111 VC 1000 HI 1001 LS 1010 GE 1011 LT 1100 GT 1101 LE 1110 AL 1111 NV <Sn> Is the 32-bit name of the first SIMD&FP source register, encoded in the "Rn" field. <Sm> Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rm" field. <Dn> Is the 64-bit name of the first SIMD&FP source register, encoded in the "Rn" field. <Dm> Is the 64-bit name of the second SIMD&FP source register, encoded in the "Rm" field. AArch64_CheckFPEnabled(); let operand1 : bits(datasize) = V{}(n); let operand2 : bits(datasize) = V{}(m); if ConditionHolds(condition) then let signal_all_nans : boolean = FALSE; flags = FPCompare{datasize}(operand1, operand2, signal_all_nans, FPCR()); end; PSTATE.[N,Z,C,V] = flags; 2026-03-26 20:27:25 2026-03_rel