FCMP Floating-point quiet compare (scalar) This instruction compares the two SIMD&FP source register values, or the first SIMD&FP source register value and zero. It writes the result to the PSTATE.{N, Z, C, V} flags. This instruction raises an Invalid Operation floating-point exception if either or both of the operands is a signaling NaN. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. The IEEE 754 standard specifies that the result of a comparison is precisely one of <, ==, > or unordered. If either or both of the operands is a NaN, they are unordered, and all three of (Operand1 < Operand2), (Operand1 == Operand2) and (Operand1 > Operand2) are false. An unordered comparison sets the PSTATE condition flags to N=0, Z=0, C=1, and V=1. If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the NZCV condition flags written by this instruction might be significantly delayed. 0 0 0 1 1 1 1 0 1 0 0 1 0 0 0 0 x 0 0 0 1 1 0 FCMP <Hn>, <Hm> 1 1 (0) (0) (0) (0) (0) 1 FCMP <Hn>, #0.0 0 0 0 FCMP <Sn>, <Sm> 0 0 (0) (0) (0) (0) (0) 1 FCMP <Sn>, #0.0 0 1 0 FCMP <Dn>, <Dm> 0 1 (0) (0) (0) (0) (0) 1 FCMP <Dn>, #0.0 if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; if ftype == '10' then EndOfDecode(Decode_UNDEF); end; if ftype == '11' && !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); end; let n : integer = UInt(Rn); let m : integer = UInt(Rm); // ignored when opc<0> == '1' let datasize : integer{} = 8 << UInt(ftype XOR '10'); let signal_all_nans : boolean = FALSE; let cmp_with_zero : boolean = (opc[0] == '1'); <Hn> For the "Half-precision" variant: is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field. <Hn> For the "Half-precision, zero" variant: is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Hm> Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field. <Sn> For the "Single-precision" variant: is the 32-bit name of the first SIMD&FP source register, encoded in the "Rn" field. <Sn> For the "Single-precision, zero" variant: is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Sm> Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rm" field. <Dn> For the "Double-precision" variant: is the 64-bit name of the first SIMD&FP source register, encoded in the "Rn" field. <Dn> For the "Double-precision, zero" variant: is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Dm> Is the 64-bit name of the second SIMD&FP source register, encoded in the "Rm" field. AArch64_CheckFPEnabled(); let operand1 : bits(datasize) = V{}(n); let operand2 : bits(datasize) = if cmp_with_zero then FPZero{datasize}('0') else V{datasize}(m); PSTATE.[N,Z,C,V] = FPCompare{datasize}(operand1, operand2, signal_all_nans, FPCR()); 2026-03-26 20:27:25 2026-03_rel