FCVTNS (vector)
Floating-point convert to signed integer, rounding to nearest with ties to even (vector)
This instruction converts a scalar or each element in a vector
from a floating-point value to a signed integer value
using the Round to Nearest rounding mode, and
writes the result to the SIMD&FP destination register.
This instruction can generate a floating-point exception.
Depending on the settings in FPCR,
the exception results in either a flag being set in FPSR
or a synchronous exception being generated.
For more information, see
Floating-point exceptions and exception traps.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
It has encodings from 4 classes:
Scalar half-precision
,
Scalar single-precision and double-precision
,
Vector half-precision
and
Vector single-precision and double-precision
0
1
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
FCVTNS <Hd>, <Hn>
if !IsFeatureImplemented(FEAT_AdvSIMD) || !IsFeatureImplemented(FEAT_FP16) then
EndOfDecode(Decode_UNDEF);
end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let esize : integer{} = 16;
let datasize : integer{} = esize;
let elements : integer = 1;
let rounding : FPRounding = FPDecodeRounding(o1::o2);
let unsigned : boolean = FALSE;
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1
1
1
1
0
0
1
0
0
0
0
1
1
0
1
0
1
0
FCVTNS <V><d>, <V><n>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let esize : integer{} = 32 << UInt(sz);
let datasize : integer{} = esize;
let elements : integer = 1;
let rounding : FPRounding = FPDecodeRounding(o1::o2);
let unsigned : boolean = FALSE;
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0
1
1
1
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
FCVTNS <Vd>.<T>, <Vn>.<T>
if !IsFeatureImplemented(FEAT_AdvSIMD) || !IsFeatureImplemented(FEAT_FP16) then
EndOfDecode(Decode_UNDEF);
end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let esize : integer{} = 16;
let datasize : integer{} = 64 << UInt(Q);
let elements : integer = datasize DIV esize;
let rounding : FPRounding = FPDecodeRounding(o1::o2);
let unsigned : boolean = FALSE;
0
0
0
1
1
1
0
0
1
0
0
0
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1
1
0
1
0
1
0
FCVTNS <Vd>.<T>, <Vn>.<T>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if sz::Q == '10' then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let esize : integer{} = 32 << UInt(sz);
let datasize : integer{} = 64 << UInt(Q);
let elements : integer = datasize DIV esize;
let rounding : FPRounding = FPDecodeRounding(o1::o2);
let unsigned : boolean = FALSE;
<Hd>
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Hn>
Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
<V>
Is a width specifier,
<d>
Is the number of the SIMD&FP destination register, encoded in the "Rd" field.
<n>
Is the number of the SIMD&FP source register, encoded in the "Rn" field.
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
For the "Vector half-precision" variant: is an arrangement specifier,
<T>
For the "Vector single-precision and double-precision" variant: is an arrangement specifier,
sz
Q
<T>
0
0
2S
0
1
4S
1
0
RESERVED
1
1
2D
<Vn>
Is the name of the SIMD&FP source register, encoded in the "Rn" field.
if elements == 1 && IsFeatureImplemented(FEAT_FPRCVT) then
AArch64_CheckFPEnabled();
else
AArch64_CheckFPAdvSIMDEnabled();
end;
let operand : bits(datasize) = V{}(n);
let merge : boolean = elements == 1 && IsMerging(FPCR());
var result : bits(128) = if merge then V{128}(d) else Zeros{128};
let fracbits : integer = 0;
var element : bits(esize);
for e = 0 to elements-1 do
element = operand[e*:esize];
result[e*:esize] = FPToFixed{esize, esize}(element, fracbits, unsigned, FPCR(), rounding);
end;
V{128}(d) = result;
2026-03-26 20:27:25
2026-03_rel