FCVTPS (scalar) Floating-point convert to signed integer, rounding toward plus infinity (scalar) This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit signed integer using the Round towards Plus Infinity rounding mode, and writes the result to the general-purpose destination register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the general-purpose register written by this instruction might be significantly delayed. 0 0 1 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 FCVTPS <Wd>, <Hn> 1 1 1 FCVTPS <Xd>, <Hn> 0 0 0 FCVTPS <Wd>, <Sn> 1 0 0 FCVTPS <Xd>, <Sn> 0 0 1 FCVTPS <Wd>, <Dn> 1 0 1 FCVTPS <Xd>, <Dn> if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; if ftype == '10' then EndOfDecode(Decode_UNDEF); end; if ftype == '11' && !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let intsize : integer{} = 32 << UInt(sf); let fltsize : integer{} = 8 << UInt(ftype XOR '10'); let rounding : FPRounding = FPRounding_POSINF; let unsigned : boolean = FALSE; <Wd> Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field. <Hn> Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Xd> Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field. <Sn> Is the 32-bit name of the SIMD&FP source register, encoded in the "Rn" field. <Dn> Is the 64-bit name of the SIMD&FP source register, encoded in the "Rn" field. AArch64_CheckFPEnabled(); let fltval : bits(fltsize) = V{}(n); let fracbits : integer = 0; X{intsize}(d) = FPToFixed{intsize, fltsize}(fltval, fracbits, unsigned, FPCR(), rounding); 2026-03-26 20:27:25 2026-03_rel