FMUL (scalar) Floating-point multiply (scalar) This instruction multiplies the floating-point values of the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exceptions and exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. 0 0 0 1 1 1 1 0 1 0 0 0 0 1 0 1 1 FMUL <Hd>, <Hn>, <Hm> 0 0 FMUL <Sd>, <Sn>, <Sm> 0 1 FMUL <Dd>, <Dn>, <Dm> if !IsFeatureImplemented(FEAT_FP) then EndOfDecode(Decode_UNDEF); end; if ftype == '10' then EndOfDecode(Decode_UNDEF); end; if ftype == '11' && !IsFeatureImplemented(FEAT_FP16) then EndOfDecode(Decode_UNDEF); end; let d : integer{} = UInt(Rd); let n : integer{} = UInt(Rn); let m : integer{} = UInt(Rm); let esize : integer{} = 8 << UInt(ftype XOR '10'); <Hd> Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Hn> Is the 16-bit name of the first SIMD&FP source register, encoded in the "Rn" field. <Hm> Is the 16-bit name of the second SIMD&FP source register, encoded in the "Rm" field. <Sd> Is the 32-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Sn> Is the 32-bit name of the first SIMD&FP source register, encoded in the "Rn" field. <Sm> Is the 32-bit name of the second SIMD&FP source register, encoded in the "Rm" field. <Dd> Is the 64-bit name of the SIMD&FP destination register, encoded in the "Rd" field. <Dn> Is the 64-bit name of the first SIMD&FP source register, encoded in the "Rn" field. <Dm> Is the 64-bit name of the second SIMD&FP source register, encoded in the "Rm" field. AArch64_CheckFPEnabled(); let operand1 : bits(esize) = V{}(n); let operand2 : bits(esize) = V{}(m); var result : bits(128) = if IsMerging(FPCR()) then V{128}(n) else Zeros{128}; result[0+:esize] = FPMul{esize}(operand1, operand2, FPCR()); V{128}(d) = result; 2026-03-26 20:27:25 2026-03_rel