FRECPX
Floating-point reciprocal exponent (scalar)
This instruction finds an approximate reciprocal exponent for the source
SIMD&FP register and writes the result to the destination SIMD&FP register.
This instruction can generate a floating-point exception.
Depending on the settings in FPCR,
the exception results in either a flag being set in FPSR
or a synchronous exception being generated.
For more information, see
Floating-point exceptions and exception traps.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
It has encodings from 2 classes:
Half-precision
and
Single-precision and double-precision
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FRECPX <Hd>, <Hn>
if !IsFeatureImplemented(FEAT_AdvSIMD) || !IsFeatureImplemented(FEAT_FP16) then
EndOfDecode(Decode_UNDEF);
end;
let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let esize : integer{} = 16;
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FRECPX <V><d>, <V><n>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let esize : integer{} = 32 << UInt(sz);
<Hd>
Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.
<Hn>
Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.
<V>
Is a width specifier,
<d>
Is the number of the SIMD&FP destination register, encoded in the "Rd" field.
<n>
Is the number of the SIMD&FP source register, encoded in the "Rn" field.
AArch64_CheckFPEnabled();
let operand : bits(esize) = V{}(n);
let merge : boolean = IsMerging(FPCR());
var result : bits(128) = if merge then V{128}(d) else Zeros{128};
result[0+:esize] = FPRecpX{esize}(operand, FPCR());
V{128}(d) = result;
2026-03-26 20:27:25
2026-03_rel