<?xml version="1.0" ?><?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?><!DOCTYPE instructionsection  PUBLIC '-//ARM//DTD instructionsection //EN'  'iform-p.dtd'><!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. --><!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. --><instructionsection id="FRINT32Z_advsimd" title="FRINT32Z (vector) -- A64" type="instruction">
  <docvars>
    <docvar key="advsimd-datatype" value="simd-single-and-double"/>
    <docvar key="advsimd-type" value="simd"/>
    <docvar key="datatype" value="single-and-double"/>
    <docvar key="instr-class" value="advsimd"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="FRINT32Z"/>
  </docvars>
  <heading>FRINT32Z (vector)</heading>
  <desc>
    <brief>
      <para>Floating-point round to 32-bit integer toward zero (vector)</para>
    </brief>
    <authored>
      <para>This instruction rounds a vector of floating-point values in the SIMD&amp;FP source register to integral floating-point
values that fit into a 32-bit integer size using the Round towards Zero rounding mode,
and writes the result to the SIMD&amp;FP destination register.</para>
      <para>A zero input returns a zero result with the same sign. When one of the result values is not numerically equal to
the corresponding input value, an Inexact exception is raised. When an input is infinite, NaN or out-of-range,
the instruction returns for the corresponding result value the most negative integer representable in the destination size,
and an Invalid Operation floating-point exception is raised.</para>
      <para>This instruction can generate a floating-point exception.
  Depending on the settings in <register_link id="AArch64-fpcr.xml" state="AArch64">FPCR</register_link>,
  the exception results in either a flag being set in <register_link id="AArch64-fpsr.xml" state="AArch64">FPSR</register_link>
  or a synchronous exception being generated.
  For more information, see
  <xref linkend="ARMARM_BEIJDDAG">Floating-point exceptions and exception traps</xref>.</para>
      <para>Depending on the settings in the <register_link id="AArch64-cpacr_el1.xml" state="AArch64">CPACR_EL1</register_link>,
  <register_link id="AArch64-cptr_el2.xml" state="AArch64">CPTR_EL2</register_link>, and <register_link id="AArch64-cptr_el3.xml" state="AArch64">CPTR_EL3</register_link> registers,
  and the current Security state and Exception level,
  an attempt to execute the instruction might be trapped.</para>
    </authored>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="Vector single-precision and double-precision" oneof="1" id="iclass_vector_single_precision_and_double_precision" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="advsimd-datatype" value="simd-single-and-double"/>
        <docvar key="advsimd-type" value="simd"/>
        <docvar key="datatype" value="single-and-double"/>
        <docvar key="instr-class" value="advsimd"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="FRINT32Z"/>
      </docvars>
      <iclassintro count="1"/>
      <arch_variants>
        <arch_variant feature="FEAT_FRINTTS" name="v8Ap5"/>
      </arch_variants>
      <regdiagram form="32" psname="A64.simd_dp.asimdmisc.FRINT32Z_asimdmisc_R" tworows="1">
        <box hibit="31" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" width="1" name="Q" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="29" name="U" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="28" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="22" width="1" name="sz" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="21" width="5" settings="5">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="16" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="12" name="op" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="FRINT32Z_asimdmisc_R" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="advsimd-type" value="simd"/>
          <docvar key="instr-class" value="advsimd"/>
          <docvar key="isa" value="A64"/>
          <docvar key="advsimd-datatype" value="simd-single-and-double"/>
          <docvar key="datatype" value="single-and-double"/>
          <docvar key="mnemonic" value="FRINT32Z"/>
        </docvars>
        <asmtemplate><text>FRINT32Z  </text><a hover="Is the name of the SIMD&amp;FP destination register, encoded in the &quot;Rd&quot; field." link="Vd">&lt;Vd&gt;</a><text>.</text><a hover="For the &quot;Single-precision and double-precision&quot; variant: is an arrangement specifier, " link="T_option__19">&lt;T&gt;</a><text>, </text><a hover="Is the name of the SIMD&amp;FP source register, encoded in the &quot;Rn&quot; field." link="Vn">&lt;Vn&gt;</a><text>.</text><a hover="For the &quot;Single-precision and double-precision&quot; variant: is an arrangement specifier, " link="T_option__19">&lt;T&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.simd_dp.asimdmisc.FRINT32Z_asimdmisc_R" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !IsFeatureImplemented(FEAT_FRINTTS) then <a link="func_EndOfDecode_1" file="shared_pseudocode.xml">EndOfDecode</a>(<a link="enum_Decode_UNDEF" file="shared_pseudocode.xml">Decode_UNDEF</a>); end;
if sz::Q == '10' then <a link="func_EndOfDecode_1" file="shared_pseudocode.xml">EndOfDecode</a>(<a link="enum_Decode_UNDEF" file="shared_pseudocode.xml">Decode_UNDEF</a>); end;
let d : integer = UInt(Rd);
let n : integer = UInt(Rn);

let esize : integer{} = 32 &lt;&lt; UInt(sz);
let datasize : integer{} = 64 &lt;&lt; UInt(Q);
let elements : integer = datasize DIV esize;
let intsize : integer{} = 32;
let rounding : <a link="type_FPRounding" file="shared_pseudocode.xml">FPRounding</a> = <a link="enum_FPRounding_ZERO" file="shared_pseudocode.xml">FPRounding_ZERO</a>;</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="FRINT32Z_asimdmisc_R" symboldefcount="1">
      <symbol link="Vd">&lt;Vd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the name of the SIMD&amp;FP destination register, encoded in the &quot;Rd&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FRINT32Z_asimdmisc_R" symboldefcount="1">
      <symbol link="T_option__19">&lt;T&gt;</symbol>
      <definition encodedin="(sz :: Q)">
        <intro>Is an arrangement specifier, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">sz</entry>
                <entry class="bitfield">Q</entry>
                <entry class="symbol">&lt;T&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">2S</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">4S</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">2D</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="FRINT32Z_asimdmisc_R" symboldefcount="1">
      <symbol link="Vn">&lt;Vn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the name of the SIMD&amp;FP source register, encoded in the &quot;Rn&quot; field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A64.simd_dp.asimdmisc.FRINT32Z_asimdmisc_R" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="func_AArch64_CheckFPAdvSIMDEnabled_0" file="shared_pseudocode.xml">AArch64_CheckFPAdvSIMDEnabled</a>();
let operand : bits(datasize) = V{}(n);
var result : bits(datasize);
var element : bits(esize);

for e = 0 to elements-1 do
    element = operand[e*:esize];
    result[e*:esize] = <a link="func_FPRoundIntN_5" file="shared_pseudocode.xml">FPRoundIntN</a>{esize}(element, FPCR(), rounding, intsize);
end;

<a link="accessor_V_2" file="shared_pseudocode.xml">V</a>{datasize}(d) = result;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-26 20:27:25</timestamp>
  <commit_id>2026-03_rel</commit_id>
</instructionsection>