<?xml version="1.0" ?><?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?><!DOCTYPE instructionsection  PUBLIC '-//ARM//DTD instructionsection //EN'  'iform-p.dtd'><!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. --><!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. --><instructionsection id="FSCALE_advsimd" title="FSCALE -- A64" type="instruction">
  <docvars>
    <docvar key="advsimd-reguse" value="3reg-same"/>
    <docvar key="advsimd-type" value="simd"/>
    <docvar key="instr-class" value="advsimd"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="FSCALE"/>
  </docvars>
  <heading>FSCALE</heading>
  <desc>
    <brief>
      <para>Floating-point adjust exponent by vector</para>
    </brief>
    <authored>
      <para>This instruction multiplies the floating-point elements of the first
source vector by 2.0 to the power of the signed integer values in the
corresponding elements of the second source vector, and places the
results in the corresponding elements of the destination vector.</para>
    </authored>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from 2 classes:</txt>
      <a href="#iclass_half_precision">Half-precision</a>
      <txt> and </txt>
      <a href="#iclass_single_precision_and_double_precision">Single-precision and double-precision</a>
    </classesintro>
    <iclass name="Half-precision" oneof="2" id="iclass_half_precision" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="advsimd-datatype" value="simd-half"/>
        <docvar key="advsimd-reguse" value="3reg-same"/>
        <docvar key="advsimd-type" value="simd"/>
        <docvar key="datatype" value="half"/>
        <docvar key="instr-class" value="advsimd"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="FSCALE"/>
        <docvar key="reguse-datatype" value="3reg-same-half"/>
      </docvars>
      <iclassintro count="1"/>
      <arch_variants>
        <arch_variant feature="FEAT_FP8" name="v9Ap5"/>
      </arch_variants>
      <regdiagram form="32" psname="A64.simd_dp.asimdsamefp16.FSCALE_asimdsamefp16_only" tworows="1">
        <box hibit="31" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" width="1" name="Q" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="29" name="U" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="28" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" name="a" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="22" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="13" width="3" name="opcode" usename="1" settings="3" psbits="xxx">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="10" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="FSCALE_asimdsamefp16_only" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="instr-class" value="advsimd"/>
          <docvar key="isa" value="A64"/>
          <docvar key="advsimd-datatype" value="simd-half"/>
          <docvar key="advsimd-reguse" value="3reg-same"/>
          <docvar key="advsimd-type" value="simd"/>
          <docvar key="datatype" value="half"/>
          <docvar key="reguse-datatype" value="3reg-same-half"/>
          <docvar key="mnemonic" value="FSCALE"/>
        </docvars>
        <asmtemplate><text>FSCALE  </text><a hover="Is the name of the SIMD&amp;FP destination register, encoded in the &quot;Rd&quot; field." link="Vd">&lt;Vd&gt;</a><text>.</text><a hover="For the &quot;Half-precision&quot; variant: is an arrangement specifier, " link="T_option__4">&lt;T&gt;</a><text>, </text><a hover="Is the name of the first SIMD&amp;FP source register, encoded in the &quot;Rn&quot; field." link="Vn__2">&lt;Vn&gt;</a><text>.</text><a hover="For the &quot;Half-precision&quot; variant: is an arrangement specifier, " link="T_option__4">&lt;T&gt;</a><text>, </text><a hover="Is the name of the second SIMD&amp;FP source register, encoded in the &quot;Rm&quot; field." link="Vm">&lt;Vm&gt;</a><text>.</text><a hover="For the &quot;Half-precision&quot; variant: is an arrangement specifier, " link="T_option__4">&lt;T&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.simd_dp.asimdsamefp16.FSCALE_asimdsamefp16_only" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !IsFeatureImplemented(FEAT_FP8) then <a link="func_EndOfDecode_1" file="shared_pseudocode.xml">EndOfDecode</a>(<a link="enum_Decode_UNDEF" file="shared_pseudocode.xml">Decode_UNDEF</a>); end;
let esize : integer{} = 16;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);
let datasize : integer{} = if Q == '1' then 128 else 64;
let elements : integer = datasize DIV esize;</pstext></ps>
      </ps_section>
    </iclass>
    <iclass name="Single-precision and double-precision" oneof="2" id="iclass_single_precision_and_double_precision" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="advsimd-datatype" value="simd-single-and-double"/>
        <docvar key="advsimd-reguse" value="3reg-same"/>
        <docvar key="advsimd-type" value="simd"/>
        <docvar key="datatype" value="single-and-double"/>
        <docvar key="instr-class" value="advsimd"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="FSCALE"/>
        <docvar key="reguse-datatype" value="3reg-same-single-and-double"/>
      </docvars>
      <iclassintro count="1"/>
      <arch_variants>
        <arch_variant feature="FEAT_FP8" name="v9Ap5"/>
      </arch_variants>
      <regdiagram form="32" psname="A64.simd_dp.asimdsame.FSCALE_asimdsame_only" tworows="1">
        <box hibit="31" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" width="1" name="Q" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="29" name="U" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="28" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" width="2" name="size" usename="1" settings="1" psbits="xx">
          <c>1</c>
          <c>x</c>
        </box>
        <box hibit="21" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="15" width="5" name="opcode" usename="1" settings="5" psbits="xxxxx">
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="10" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="FSCALE_asimdsame_only" oneofinclass="1" oneof="2" label="">
        <docvars>
          <docvar key="instr-class" value="advsimd"/>
          <docvar key="isa" value="A64"/>
          <docvar key="advsimd-datatype" value="simd-single-and-double"/>
          <docvar key="advsimd-reguse" value="3reg-same"/>
          <docvar key="advsimd-type" value="simd"/>
          <docvar key="datatype" value="single-and-double"/>
          <docvar key="reguse-datatype" value="3reg-same-single-and-double"/>
          <docvar key="mnemonic" value="FSCALE"/>
        </docvars>
        <asmtemplate><text>FSCALE  </text><a hover="Is the name of the SIMD&amp;FP destination register, encoded in the &quot;Rd&quot; field." link="Vd">&lt;Vd&gt;</a><text>.</text><a hover="For the &quot;Single-precision and double-precision&quot; variant: is an arrangement specifier, " link="T_option__19">&lt;T&gt;</a><text>, </text><a hover="Is the name of the first SIMD&amp;FP source register, encoded in the &quot;Rn&quot; field." link="Vn__2">&lt;Vn&gt;</a><text>.</text><a hover="For the &quot;Single-precision and double-precision&quot; variant: is an arrangement specifier, " link="T_option__19">&lt;T&gt;</a><text>, </text><a hover="Is the name of the second SIMD&amp;FP source register, encoded in the &quot;Rm&quot; field." link="Vm">&lt;Vm&gt;</a><text>.</text><a hover="For the &quot;Single-precision and double-precision&quot; variant: is an arrangement specifier, " link="T_option__19">&lt;T&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.simd_dp.asimdsame.FSCALE_asimdsame_only" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !IsFeatureImplemented(FEAT_FP8) then <a link="func_EndOfDecode_1" file="shared_pseudocode.xml">EndOfDecode</a>(<a link="enum_Decode_UNDEF" file="shared_pseudocode.xml">Decode_UNDEF</a>); end;
if Q == '0' &amp;&amp; size == '11' then <a link="func_EndOfDecode_1" file="shared_pseudocode.xml">EndOfDecode</a>(<a link="enum_Decode_UNDEF" file="shared_pseudocode.xml">Decode_UNDEF</a>); end;
let esize : integer{} = 8 &lt;&lt; UInt(size);
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);
let datasize : integer{} = if Q == '1' then 128 else 64;
let elements : integer = datasize DIV esize;</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="FSCALE_asimdsamefp16_only, FSCALE_asimdsame_only" symboldefcount="1">
      <symbol link="Vd">&lt;Vd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the name of the SIMD&amp;FP destination register, encoded in the &quot;Rd&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FSCALE_asimdsamefp16_only" symboldefcount="1">
      <symbol link="T_option__4">&lt;T&gt;</symbol>
      <definition encodedin="Q">
        <intro>For the &quot;Half-precision&quot; variant: is an arrangement specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">Q</entry>
                <entry class="symbol">&lt;T&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">4H</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">8H</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="FSCALE_asimdsame_only" symboldefcount="2">
      <symbol link="T_option__19">&lt;T&gt;</symbol>
      <definition encodedin="(size[0] :: Q)">
        <intro>For the &quot;Single-precision and double-precision&quot; variant: is an arrangement specifier, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">size[0]</entry>
                <entry class="bitfield">Q</entry>
                <entry class="symbol">&lt;T&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">2S</entry>
              </row>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">4S</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">2D</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="FSCALE_asimdsamefp16_only, FSCALE_asimdsame_only" symboldefcount="1">
      <symbol link="Vn__2">&lt;Vn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the name of the first SIMD&amp;FP source register, encoded in the &quot;Rn&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="FSCALE_asimdsamefp16_only, FSCALE_asimdsame_only" symboldefcount="1">
      <symbol link="Vm">&lt;Vm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the name of the second SIMD&amp;FP source register, encoded in the &quot;Rm&quot; field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A64.simd_dp.asimdsamefp16.FSCALE_asimdsamefp16_only" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="func_AArch64_CheckFPAdvSIMDEnabled_0" file="shared_pseudocode.xml">AArch64_CheckFPAdvSIMDEnabled</a>();
let operand1 : bits(datasize) = V{}(n);
let operand2 : bits(datasize) = V{}(m);
var result : bits(datasize);

for e = 0 to elements-1 do
    let op1 : bits(esize) = operand1[e*:esize];
    let op2 : integer     = SInt(operand2[e*:esize]);
    result[e*:esize] = <a link="func_FPScale_4" file="shared_pseudocode.xml">FPScale</a>{esize}(op1, op2, FPCR());
end;

<a link="accessor_V_2" file="shared_pseudocode.xml">V</a>{datasize}(d) = result;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-26 20:27:25</timestamp>
  <commit_id>2026-03_rel</commit_id>
</instructionsection>