<?xml version="1.0" ?><?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?><!DOCTYPE instructionsection  PUBLIC '-//ARM//DTD instructionsection //EN'  'iform-p.dtd'><!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. --><!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. --><instructionsection id="GCSSTTR" title="GCSSTTR -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="GCSSTTR"/>
  </docvars>
  <heading>GCSSTTR</heading>
  <desc>
    <brief>
      <para>Guarded Control Stack store register (unprivileged)</para>
    </brief>
    <authored>
      <para>This instruction stores a
doubleword from a register to memory. The address that
is used for the store is calculated from a base register.</para>
      <para>Explicit Memory  effects produced by the instruction behave as if the instruction was
  executed at EL0 if the <xref linkend="ARMARM_Effective_value">Effective value</xref> of
  PSTATE.UAO is 0 and either:</para>
      <list type="unordered">
        <listitem>
          <content>The instruction is executed at EL1 and the <xref linkend="ARMARM_Effective_value">Effective value</xref> of <register_link id="AArch64-hcr_el2.xml" state="AArch64">HCR_EL2</register_link>.{NV1, NV} is not {1, 1}.</content>
        </listitem>
        <listitem>
          <content>The instruction is executed at EL2 when the <xref linkend="ARMARM_Effective_value">Effective value</xref>
  of <register_link id="AArch64-hcr_el2.xml" state="AArch64">HCR_EL2()</register_link>.{E2H, TGE} is '11'.</content>
        </listitem>
      </list>
      <para>Otherwise, the Explicit Memory  effects operate with the restrictions determined by
  the Exception level at which the instruction is executed.</para>
    </authored>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="Integer" oneof="1" id="iclass_integer" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="GCSSTTR"/>
      </docvars>
      <iclassintro count="1"/>
      <arch_variants>
        <arch_variant feature="FEAT_GCS" name="v9Ap4"/>
      </arch_variants>
      <regdiagram form="32" psname="A64.ldst.ldst_gcs.GCSSTTR_64_ldst_gcs" tworows="1">
        <box hibit="31" width="4" settings="4">
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="27" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="26" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="25" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="10" settings="10">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="14" width="3" name="opc" usename="1" settings="3" psbits="xxx">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="GCSSTTR_64_ldst_gcs" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="GCSSTTR"/>
        </docvars>
        <asmtemplate><text>GCSSTTR  </text><a hover="Is the 64-bit name of the general-purpose register to be transferred, encoded in the &quot;Rt&quot; field." link="XtOrXZR__11">&lt;Xt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.ldst.ldst_gcs.GCSSTTR_64_ldst_gcs" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !IsFeatureImplemented(FEAT_GCS) then <a link="func_EndOfDecode_1" file="shared_pseudocode.xml">EndOfDecode</a>(<a link="enum_Decode_UNDEF" file="shared_pseudocode.xml">Decode_UNDEF</a>); end;
let t : integer{} = UInt(Rt);
let n : integer{} = UInt(Rn);</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="GCSSTTR_64_ldst_gcs" symboldefcount="1">
      <symbol link="XtOrXZR__11">&lt;Xt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 64-bit name of the general-purpose register to be transferred, encoded in the &quot;Rt&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="GCSSTTR_64_ldst_gcs" symboldefcount="1">
      <symbol link="XnSP_option">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A64.ldst.ldst_gcs.GCSSTTR_64_ldst_gcs" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">var address : bits(64);

let effective_el : bits(2) = if <a link="func_AArch64_IsUnprivAccessPriv_0" file="shared_pseudocode.xml">AArch64_IsUnprivAccessPriv</a>() then <a link="global_PSTATE" file="shared_pseudocode.xml">PSTATE</a>.EL else <a link="global_EL0" file="shared_pseudocode.xml">EL0</a>;

if effective_el == <a link="global_PSTATE" file="shared_pseudocode.xml">PSTATE</a>.EL then
    <a link="func_CheckGCSSTREnabled_0" file="shared_pseudocode.xml">CheckGCSSTREnabled</a>();
end;

let privileged : boolean = effective_el != <a link="global_EL0" file="shared_pseudocode.xml">EL0</a>;
let accdesc : <a link="type_AccessDescriptor" file="shared_pseudocode.xml">AccessDescriptor</a> = <a link="func_CreateAccDescGCS_2" file="shared_pseudocode.xml">CreateAccDescGCS</a>(<a link="enum_MemOp_STORE" file="shared_pseudocode.xml">MemOp_STORE</a>, privileged);

if n == 31 then
    <a link="func_CheckSPAlignment_0" file="shared_pseudocode.xml">CheckSPAlignment</a>();
    address = <a link="accessor_SP_1" file="shared_pseudocode.xml">SP</a>{64}();
else
    address = <a link="accessor_X_2" file="shared_pseudocode.xml">X</a>{64}(n);
end;

<a link="accessor_Mem_3" file="shared_pseudocode.xml">Mem</a>{64}(address, accdesc) = <a link="accessor_X_2" file="shared_pseudocode.xml">X</a>{64}(t);</pstext></ps>
  </ps_section>
  <timestamp>2026-03-26 20:27:25</timestamp>
  <commit_id>2026-03_rel</commit_id>
</instructionsection>