IC Instruction cache operation For more information, see op0 == 0b01, cache maintenance, TLB maintenance, address translation, prediction restriction, BRBE, Trace Extension, and Guarded Control Stack instructions. SYS 1 1 0 1 0 1 0 1 0 0 0 0 1 0 1 1 1 IC <ic_op>{, <Xt>} SYS #<op1>, C7, <Cm>, #<op2>{, <Xt>} SysOp(op1, '0111', CRm, op2) == Sys_IC <ic_op> Is an IC operation name, as listed for the IC system instruction pages, op1 CRm op2 <ic_op> Description 000 0001 000 IALLUIS For more information, see IC IALLUIS. 000 0101 000 IALLU For more information, see IC IALLU. 011 0101 001 IVAU For more information, see IC IVAU. <Xt> Is the 64-bit name of the optional general-purpose source register, defaulting to '11111', encoded in the "Rt" field. 2026-03-26 20:27:25 2026-03_rel