<?xml version="1.0" ?><?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?><!DOCTYPE instructionsection  PUBLIC '-//ARM//DTD instructionsection //EN'  'iform-p.dtd'><!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. --><!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. --><instructionsection id="LDLAR" title="LDLAR -- A64" type="instruction">
  <docvars>
    <docvar key="address-form" value="base-register"/>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="LDLAR"/>
  </docvars>
  <heading>LDLAR</heading>
  <desc>
    <brief>
      <para>Load LOAcquire register</para>
    </brief>
    <authored>
      <para>This instruction loads a 32-bit word or 64-bit doubleword
from memory, and writes
it to a register.</para>
      <para>If the destination register is not one of <value>WZR</value> or <value>XZR</value>,
<instruction>LDLAR</instruction> loads from memory with Acquire semantics.</para>
      <para>For more information about memory ordering semantics, see <xref linkend="ARMARM_BEIJDIJG">Load LOAcquire, Store LORelease</xref>
and <xref linkend="ARMARM_BEIHCHEF">Load-Acquire, Load-AcquirePC, and Store-Release</xref>.</para>
      <para>For information about addressing modes, see
<xref linkend="ARMARM_CHDIIIBB">Load/Store addressing modes</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <operationalnote>
      <operationalnote_content>
        <para>This instruction is a data-independent-time instruction as described in <xref linkend="ARMARM_BEICCDDAB3">About PSTATE.DIT</xref>.</para>
      </operationalnote_content>
    </operationalnote>
  </operationalnotes>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="No offset" oneof="1" id="iclass_no_offset" no_encodings="2" isa="A64">
      <docvars>
        <docvar key="address-form" value="base-register"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="LDLAR"/>
      </docvars>
      <iclassintro count="2"/>
      <arch_variants>
        <arch_variant feature="FEAT_LOR" name="v8Ap1 &amp;&amp; PROFILE_A"/>
      </arch_variants>
      <regdiagram form="32" psname="A64.ldst.ldstord.LDLAR_LR32_ldstord" tworows="1">
        <box hibit="31" width="2" name="size" usename="1" settings="1" psbits="xx">
          <c>1</c>
          <c>x</c>
        </box>
        <box hibit="29" width="7" settings="7">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="L" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="21" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="Rs" usename="1" settings="5" psbits="xxxxx">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="15" name="o0" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="14" width="5" name="Rt2" usename="1" settings="5" psbits="xxxxx">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="LDLAR_LR32_ldstord" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="size == 10">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="address-form" value="base-register"/>
          <docvar key="address-form-reg-type" value="base-register-32-reg"/>
          <docvar key="atomic-ops" value="LDLAR-32-reg"/>
          <docvar key="reg-type" value="32-reg"/>
          <docvar key="mnemonic" value="LDLAR"/>
        </docvars>
        <box hibit="31" width="2" name="size">
          <c/>
          <c>0</c>
        </box>
        <asmtemplate><text>LDLAR  </text><a hover="Is the 32-bit name of the general-purpose register to be transferred, encoded in the &quot;Rt&quot; field." link="WtOrWZR__4">&lt;Wt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>{, #0}]</text></asmtemplate>
      </encoding>
      <encoding name="LDLAR_LR64_ldstord" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="size == 11">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="address-form" value="base-register"/>
          <docvar key="address-form-reg-type" value="base-register-64-reg"/>
          <docvar key="atomic-ops" value="LDLAR-64-reg"/>
          <docvar key="reg-type" value="64-reg"/>
          <docvar key="mnemonic" value="LDLAR"/>
        </docvars>
        <box hibit="31" width="2" name="size">
          <c/>
          <c>1</c>
        </box>
        <asmtemplate><text>LDLAR  </text><a hover="Is the 64-bit name of the general-purpose register to be transferred, encoded in the &quot;Rt&quot; field." link="XtOrXZR__11">&lt;Xt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>{, #0}]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.ldst.ldstord.LDLAR_LR32_ldstord" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !IsFeatureImplemented(FEAT_LOR) then <a link="func_EndOfDecode_1" file="shared_pseudocode.xml">EndOfDecode</a>(<a link="enum_Decode_UNDEF" file="shared_pseudocode.xml">Decode_UNDEF</a>); end;
let t : integer{} = UInt(Rt);
let n : integer{} = UInt(Rn);
let elsize : integer{} = 8 &lt;&lt; UInt(size);
let regsize : integer{} = if elsize == 64 then 64 else 32;
let acquire : boolean = TRUE;
let tagchecked : boolean = n != 31;</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDLAR_LR32_ldstord" symboldefcount="1">
      <symbol link="WtOrWZR__4">&lt;Wt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 32-bit name of the general-purpose register to be transferred, encoded in the &quot;Rt&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDLAR_LR32_ldstord, LDLAR_LR64_ldstord" symboldefcount="1">
      <symbol link="XnSP_option">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDLAR_LR64_ldstord" symboldefcount="1">
      <symbol link="XtOrXZR__11">&lt;Xt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 64-bit name of the general-purpose register to be transferred, encoded in the &quot;Rt&quot; field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A64.ldst.ldstord.LDLAR_LR32_ldstord" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">var address : bits(64);
let dbytes : integer{} = elsize DIV 8;

let accdesc : <a link="type_AccessDescriptor" file="shared_pseudocode.xml">AccessDescriptor</a> = <a link="func_CreateAccDescLOR_4" file="shared_pseudocode.xml">CreateAccDescLOR</a>(<a link="enum_MemOp_LOAD" file="shared_pseudocode.xml">MemOp_LOAD</a>, tagchecked, acquire, t);

if n == 31 then
    <a link="func_CheckSPAlignment_0" file="shared_pseudocode.xml">CheckSPAlignment</a>();
    address = <a link="accessor_SP_1" file="shared_pseudocode.xml">SP</a>{64}();
else
    address = <a link="accessor_X_2" file="shared_pseudocode.xml">X</a>{64}(n);
end;

let data : bits(elsize) = <a link="accessor_Mem_3" file="shared_pseudocode.xml">Mem</a>{elsize}(address, accdesc);
<a link="accessor_X_2" file="shared_pseudocode.xml">X</a>{regsize}(t) = ZeroExtend{regsize}(data);</pstext></ps>
  </ps_section>
  <timestamp>2026-03-26 20:27:25</timestamp>
  <commit_id>2026-03_rel</commit_id>
</instructionsection>