<?xml version="1.0" ?><?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?><!DOCTYPE instructionsection  PUBLIC '-//ARM//DTD instructionsection //EN'  'iform-p.dtd'><!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. --><!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. --><instructionsection id="LDRSW_lit" title="LDRSW (literal) -- A64" type="instruction">
  <docvars>
    <docvar key="address-form" value="literal"/>
    <docvar key="address-form-reg-type" value="literal-64-reg"/>
    <docvar key="atomic-ops" value="LDRSW-64-reg"/>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="LDRSW"/>
    <docvar key="offset-type" value="off19s"/>
    <docvar key="reg-type" value="64-reg"/>
  </docvars>
  <heading>LDRSW (literal)</heading>
  <desc>
    <brief>
      <para>Load register signed word (literal)</para>
    </brief>
    <authored>
      <para>This instruction calculates an address
from the PC value and an immediate offset, loads a
word from memory, and
writes it to a register. For information about addressing modes, see
<xref linkend="ARMARM_CHDIIIBB">Load/Store addressing modes</xref>.</para>
    </authored>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="Literal" oneof="1" id="iclass_literal" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="address-form" value="literal"/>
        <docvar key="address-form-reg-type" value="literal-64-reg"/>
        <docvar key="atomic-ops" value="LDRSW-64-reg"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="LDRSW"/>
        <docvar key="offset-type" value="off19s"/>
        <docvar key="reg-type" value="64-reg"/>
      </docvars>
      <iclassintro count="1"/>
      <regdiagram form="32" psname="A64.ldst.loadlit.LDRSW_64_loadlit" tworows="1">
        <box hibit="31" width="2" name="opc" usename="1" settings="2" psbits="xx">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="29" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="27" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="26" name="VR" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="25" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="24" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" width="19" name="imm19" usename="1">
          <c colspan="19"/>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="LDRSW_64_loadlit" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="address-form" value="literal"/>
          <docvar key="address-form-reg-type" value="literal-64-reg"/>
          <docvar key="atomic-ops" value="LDRSW-64-reg"/>
          <docvar key="offset-type" value="off19s"/>
          <docvar key="reg-type" value="64-reg"/>
          <docvar key="mnemonic" value="LDRSW"/>
        </docvars>
        <asmtemplate><text>LDRSW  </text><a hover="Is the 64-bit name of the general-purpose register to be loaded, encoded in the &quot;Rt&quot; field." link="XtOrXZR__8">&lt;Xt&gt;</a><text>, </text><a hover="Is the program label from which the data is to be loaded. Its offset from the address of this instruction, in the range +/-1MB, is encoded as &quot;imm19&quot; times 4." link="imm19_offset__2">&lt;label&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.ldst.loadlit.LDRSW_64_loadlit" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let t : integer{} = UInt(Rt);
let nontemporal : boolean = FALSE;
let tagchecked : boolean = FALSE;

let offset : bits(64) = SignExtend{}(imm19::'00');</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="LDRSW_64_loadlit" symboldefcount="1">
      <symbol link="XtOrXZR__8">&lt;Xt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 64-bit name of the general-purpose register to be loaded, encoded in the &quot;Rt&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="LDRSW_64_loadlit" symboldefcount="1">
      <symbol link="imm19_offset__2">&lt;label&gt;</symbol>
      <account encodedin="imm19">
        <intro>
          <para>Is the program label from which the data is to be loaded. Its offset from the address of this instruction, in the range +/-1MB, is encoded as &quot;imm19&quot; times 4.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A64.ldst.loadlit.LDRSW_64_loadlit" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">let address : bits(64) = <a link="func_PC64_0" file="shared_pseudocode.xml">PC64</a>() + offset;
let privileged : boolean = <a link="global_PSTATE" file="shared_pseudocode.xml">PSTATE</a>.EL != <a link="global_EL0" file="shared_pseudocode.xml">EL0</a>;
let accdesc : <a link="type_AccessDescriptor" file="shared_pseudocode.xml">AccessDescriptor</a> = <a link="func_CreateAccDescGPR_5" file="shared_pseudocode.xml">CreateAccDescGPR</a>(<a link="enum_MemOp_LOAD" file="shared_pseudocode.xml">MemOp_LOAD</a>, nontemporal, privileged,
                                                  tagchecked, t);

let data : bits(32) = <a link="accessor_Mem_3" file="shared_pseudocode.xml">Mem</a>{32}(address, accdesc);
<a link="accessor_X_2" file="shared_pseudocode.xml">X</a>{64}(t) = SignExtend{64}(data);</pstext></ps>
  </ps_section>
  <timestamp>2026-03-26 20:27:25</timestamp>
  <commit_id>2026-03_rel</commit_id>
</instructionsection>