LDSET, LDSETA, LDSETAL, LDSETL Atomic bit set on word or doubleword This instruction atomically loads a 32-bit word or 64-bit doubleword from memory, performs a bitwise OR with the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register. If the destination register is not one of WZR or XZR, LDSETA and LDSETAL load from memory with acquire semantics. LDSETL and LDSETAL store to memory with release semantics. LDSET has neither acquire nor release semantics. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes. This instruction is a data-independent-time instruction as described in About PSTATE.DIT. This instruction is used by the alias STSET, STSETL A == '0' && Rt == '11111' See below for details of when the alias is preferred. 1 x 1 1 1 0 0 0 1 0 0 1 1 0 0 0 0 0 LDSET <Ws>, <Wt>, [<Xn|SP>] 0 1 0 LDSETA <Ws>, <Wt>, [<Xn|SP>] 0 1 1 LDSETAL <Ws>, <Wt>, [<Xn|SP>] 0 0 1 LDSETL <Ws>, <Wt>, [<Xn|SP>] 1 0 0 LDSET <Xs>, <Xt>, [<Xn|SP>] 1 1 0 LDSETA <Xs>, <Xt>, [<Xn|SP>] 1 1 1 LDSETAL <Xs>, <Xt>, [<Xn|SP>] 1 0 1 LDSETL <Xs>, <Xt>, [<Xn|SP>] if !IsFeatureImplemented(FEAT_LSE) then EndOfDecode(Decode_UNDEF); end; let s : integer{} = UInt(Rs); let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let datasize : integer{} = 8 << UInt(size); let regsize : integer{} = if datasize == 64 then 64 else 32; let acquire : boolean = A == '1' && Rt != '11111'; let release : boolean = R == '1'; let tagchecked : boolean = n != 31; <Ws> Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field. <Wt> Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field. <Xn|SP> Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. <Xs> Is the 64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field. <Xt> Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field. Alias Conditions var address : bits(64); let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescAtomicOp(MemAtomicOp_ORR, acquire, release, tagchecked, privileged, t, s); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; let comparevalue : bits(datasize) = ARBITRARY : bits(datasize); // Irrelevant when not executing CAS let value : bits(datasize) = X{datasize}(s); let data : bits(datasize) = MemAtomic{}(address, comparevalue, value, accdesc); if t != 31 then X{regsize}(t) = ZeroExtend{regsize}(data); end; 2026-03-26 20:27:25 2026-03_rel