LDTXR
Load unprivileged exclusive register
This instruction derives an address from a base register
value, loads a 32-bit word or a 64-bit doubleword from memory,
and writes it to
a register. The memory access is atomic.
The PE marks the physical address being accessed as an exclusive access.
This exclusive access mark is checked by Store Exclusive instructions. See
Synchronization and semaphores.
Explicit Memory effects produced by the instruction behave as if the instruction was
executed at EL0 if the Effective value of
PSTATE.UAO is 0 and either:
The instruction is executed at EL1.
The instruction is executed at EL2 when the Effective value
of HCR_EL2().{E2H, TGE} is '11'.
Otherwise, the Explicit Memory effects operate with the restrictions determined by
the Exception level at which the instruction is executed.
For the purposes of the Exclusives monitors, and the forward progress guarantees for
Load-Exclusive and Store-Exclusive loops, LDTXR is
equivalent to LDXR.
For information about addressing modes, see
Load/Store addressing modes.
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
1
0
0
1
0
0
1
0
1
0
(1)
(1)
(1)
(1)
(1)
0
(1)
(1)
(1)
(1)
(1)
0
LDTXR <Wt>, [<Xn|SP>{, #0}]
1
LDTXR <Xt>, [<Xn|SP>{, #0}]
if !IsFeatureImplemented(FEAT_LSUI) then EndOfDecode(Decode_UNDEF); end;
let t : integer{} = UInt(Rt);
let n : integer{} = UInt(Rn);
let elsize : integer{} = 32 << UInt(sz);
let regsize : integer{} = if elsize == 64 then 64 else 32;
let acqrel : boolean = FALSE;
let tagchecked : boolean = n != 31;
<Wt>
Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<Xt>
Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
var address : bits(64);
var data : bits(elsize);
let dbytes : integer{} = elsize DIV 8;
let privileged : boolean = AArch64_IsUnprivAccessPriv();
let accdesc : AccessDescriptor = CreateAccDescExLDST(MemOp_LOAD, acqrel, tagchecked,
privileged, t);
if n == 31 then
CheckSPAlignment();
address = SP{64}();
else
address = X{64}(n);
end;
AArch64_SetExclusiveMonitors(address, dbytes, accdesc);
data = Mem{elsize}(address, accdesc);
X{regsize}(t) = ZeroExtend{regsize}(data);
2026-03-26 20:27:25
2026-03_rel