<?xml version="1.0" ?><?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?><!DOCTYPE instructionsection  PUBLIC '-//ARM//DTD instructionsection //EN'  'iform-p.dtd'><!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. --><!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. --><instructionsection id="pfalse_p" title="PFALSE -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="sve"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="PFALSE"/>
  </docvars>
  <heading>PFALSE</heading>
  <desc>
    <brief>
      <para>Set all predicate elements to false</para>
    </brief>
    <authored>
      <para>This instruction sets all elements in the destination predicate to false.</para>
      <para>For programmer convenience, an assembler
      must also accept predicate-as-counter register name for the
      destination predicate register.</para>
    </authored>
    <predicated>False</predicated>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="instr-class" value="sve"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="PFALSE"/>
      </docvars>
      <iclassintro count="1"/>
      <arch_variants>
        <arch_variant feature="FEAT_SVE || FEAT_SME" name="(v8Ap2 &amp;&amp; PROFILE_A) || (v9Ap2 &amp;&amp; PROFILE_A)"/>
      </arch_variants>
      <regdiagram form="32" psname="A64.sve.sve_pred_gen_d.sve_int_pfalse.pfalse_p_" tworows="1">
        <box hibit="31" width="3" settings="3">
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="28" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="24" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="23" name="op" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="22" name="S" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="21" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="19" width="4" settings="4">
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="13" width="3" settings="3">
          <c>1</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="10" width="2" settings="2">
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="8" width="4" settings="4">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="4" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="3" width="4" name="Pd" usename="1">
          <c colspan="4"/>
        </box>
      </regdiagram>
      <encoding name="pfalse_p_" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="instr-class" value="sve"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="PFALSE"/>
        </docvars>
        <asmtemplate><text>PFALSE  </text><a hover="Is the name of the destination scalable predicate register, encoded in the &quot;Pd&quot; field." link="Pd">&lt;Pd&gt;</a><text>.B</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.sve.sve_pred_gen_d.sve_int_pfalse.pfalse_p_" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !IsFeatureImplemented(FEAT_SVE) &amp;&amp; !IsFeatureImplemented(FEAT_SME) then
    <a link="func_EndOfDecode_1" file="shared_pseudocode.xml">EndOfDecode</a>(<a link="enum_Decode_UNDEF" file="shared_pseudocode.xml">Decode_UNDEF</a>);
end;
let d : integer = UInt(Pd);</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="pfalse_p_" symboldefcount="1">
      <symbol link="Pd">&lt;Pd&gt;</symbol>
      <account encodedin="Pd">
        <intro>
          <para>Is the name of the destination scalable predicate register, encoded in the &quot;Pd&quot; field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A64.sve.sve_pred_gen_d.sve_int_pfalse.pfalse_p_" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="func_CheckSVEEnabled_0" file="shared_pseudocode.xml">CheckSVEEnabled</a>();
let VL : integer{} = <a link="func_CurrentVL_0" file="shared_pseudocode.xml">CurrentVL</a>();
let PL : integer{} = VL DIV 8;
<a link="accessor_P_2" file="shared_pseudocode.xml">P</a>{PL}(d) = Zeros{PL};</pstext></ps>
  </ps_section>
  <timestamp>2026-03-26 20:27:25</timestamp>
  <commit_id>2026-03_rel</commit_id>
</instructionsection>