PRFM (register)
Prefetch memory (register)
This instruction signals the memory system that data memory
accesses from a specified address are likely to occur in the near
future. The address for data memory accesses is calculated from a
base register value and an offset register value. The offset
register value can optionally be shifted and extended.
The memory system can respond by taking actions that are
expected to speed up the memory accesses when they do occur, such as
making the cache line containing the specified address available at
the level of cache specified by the instruction.
The <prfop> operand specifies the prefetch hint as follows:
Access type:
PLD for prefetch for load.
PLI for prefetch for execute.
PST for prefetch for store.
Target cache level:
L1 for Level 1 cache.
L2 for Level 2 cache.
L3 for Level 3 cache.
When FEAT_PRFMSLC is implemented, SLC for system level cache.
Policy:
KEEP for retained or temporal prefetch, allocated in the cache normally.
STRM for streaming or non-temporal prefetch, for data that is used only once.
The effect of a PRFM instruction is
IMPLEMENTATION DEFINED. For more information,
see Prefetch memory.
For information about addressing modes, see
Load/Store addressing modes.
1
1
1
1
1
0
0
0
1
0
1
x
1
x
1
0
!= 11xxx
PRFM (<prfop>|#<imm5>), [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
if option[1] == '0' then EndOfDecode(Decode_UNDEF); end; // sub-word index
let extend_type : ExtendType = DecodeRegExtend(option);
let shift : integer{} = if S == '1' then 3 else 0;
let n : integer = UInt(Rn);
let t : integer = UInt(Rt);
let m : integer = UInt(Rm);
let nontemporal : boolean = FALSE;
let tagchecked : boolean = FALSE;
<prfop>
Is the prefetch operation,
Rt
<prfop>
Architectural Feature
00000
PLDL1KEEP
00001
PLDL1STRM
00010
PLDL2KEEP
00011
PLDL2STRM
00100
PLDL3KEEP
00101
PLDL3STRM
00110
PLDSLCKEEP
00111
PLDSLCSTRM
01000
PLIL1KEEP
01001
PLIL1STRM
01010
PLIL2KEEP
01011
PLIL2STRM
01100
PLIL3KEEP
01101
PLIL3STRM
01110
PLISLCKEEP
01111
PLISLCSTRM
10000
PSTL1KEEP
10001
PSTL1STRM
10010
PSTL2KEEP
10011
PSTL2STRM
10100
PSTL3KEEP
10101
PSTL3STRM
10110
PSTSLCKEEP
10111
PSTSLCSTRM
For other encodings of the "Rt" field, use <imm5>.
<imm5>
Is the prefetch operation encoding as an immediate, in the range 0 to 31, encoded in the "Rt" field.
This syntax is only for encodings that are not accessible using <prfop>.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<Wm>
When option<0> is set to 0, is the 32-bit name of the general-purpose index register, encoded in the "Rm" field.
<Xm>
When option<0> is set to 1, is the 64-bit name of the general-purpose index register, encoded in the "Rm" field.
<extend>
Is the index extend/shift specifier, defaulting to LSL, and which must be omitted for the LSL option when <amount> is omitted,
option
<extend>
010
UXTW
011
LSL
110
SXTW
111
SXTX
<amount>
Is the index shift amount, optional only when <extend> is not LSL. Where it is permitted to be optional, it defaults to #0. It is
var address : bits(64);
let offset : bits(64) = ExtendReg{}(m, extend_type, shift);
let privileged : boolean = PSTATE.EL != EL0;
let accdesc : AccessDescriptor = CreateAccDescGPR(MemOp_PREFETCH, nontemporal, privileged,
tagchecked, t);
if n == 31 then
address = SP{64}();
else
address = X{64}(n);
end;
address = AddressAdd(address, offset, accdesc);
let supports_ir : boolean = FALSE;
Prefetch(address, t[4:0], supports_ir);
2026-03-26 20:27:25
2026-03_rel