PSB Profiling synchronization barrier This instruction is a barrier that ensures that all existing profiling data for the current PE has been formatted, and profiling buffer addresses have been translated such that all writes to the profiling buffer have been initiated. A following DSB instruction completes when the writes to the profiling buffer have completed. If FEAT_SPE is not implemented, this instruction executes as a NOP. 1 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 1 1 1 1 1 PSB CSYNC if !IsFeatureImplemented(FEAT_SPE) then EndOfDecode(Decode_NOP); end; if IsFeatureImplemented(FEAT_FGT) && IsFeatureImplemented(FEAT_SPEv1p5) then let trap_to_el2 : boolean = (PSTATE.EL IN {EL0, EL1} && EL2Enabled() && !IsInHost() && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().PSBCSYNC == '1'); if trap_to_el2 then let target_el : bits(2) = EL2; let iss : bits(25) = 0x3[24:0]; AArch64_OtherInstrTrap(target_el, iss); end; end; ProfilingSynchronizationBarrier(); 2026-03-26 20:27:25 2026-03_rel