PSSBB Physical speculative store bypass barrier This instruction is a memory barrier that prevents speculative loads from bypassing earlier stores to the same physical address under certain conditions. For more information and details of the semantics, see Physical Speculative Store Bypass Barrier (PSSBB). DSB 1 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 PSSBB DSB #4 Unconditionally 2026-03-26 20:27:25 2026-03_rel