<?xml version="1.0" ?><?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?><!DOCTYPE instructionsection  PUBLIC '-//ARM//DTD instructionsection //EN'  'iform-p.dtd'><!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. --><!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. --><instructionsection id="RCWSCAS" title="RCWSCAS, RCWSCASA, RCWSCASAL, RCWSCASL -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="A64"/>
  </docvars>
  <heading>RCWSCAS, RCWSCASA, RCWSCASAL, RCWSCASL</heading>
  <desc>
    <brief>
      <para>Read check write software compare and swap doubleword in memory</para>
    </brief>
    <authored>
      <para>This instruction reads a 64-bit doubleword
from memory, and compares it against the value held in a register. If the comparison
is equal, the value in a second register is conditionally written to memory.
Storing back to memory is conditional on RCW Checks and RCWS Checks. 
  If the compare fails, the RCW
        Checks fail, or the RCWS Checks fail, the architecture permits writing the value read from the
  location to memory. If the write is performed, the read and the write occur
  atomically such that no other
  modification of the memory location can take place between the read and the write.
  This instruction updates the condition flags based on the result of the
  update of memory.</para>
      <list type="unordered">
        <listitem>
          <content>If the destination register is not <value>XZR</value>, <instruction>RCWSCASA</instruction> and <instruction>RCWSCASAL</instruction> load from memory with acquire semantics.</content>
        </listitem>
        <listitem>
          <content>
            <instruction>RCWSCASL</instruction> and <instruction>RCWSCASAL</instruction> store to memory with release semantics.</content>
        </listitem>
        <listitem>
          <content>
            <instruction>RCWSCAS</instruction> has neither acquire nor release semantics.</content>
        </listitem>
      </list>
      <note>
        <para>This instruction is for performing atomic updates of translation table entries and not
for general use.</para>
      </note>
    </authored>
  </desc>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="Integer" oneof="1" id="iclass_integer" no_encodings="4" isa="A64">
      <docvars>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A64"/>
      </docvars>
      <iclassintro count="4"/>
      <arch_variants>
        <arch_variant feature="FEAT_THE" name="v8Ap9"/>
      </arch_variants>
      <regdiagram form="32" psname="A64.ldst.rcwcomswap.RCWSCAS_C64_rcwcomswap" tworows="1">
        <box hibit="31" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" name="S" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="29" width="6" settings="6">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="23" width="1" name="A" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="22" width="1" name="R" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="21" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rs" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="15" width="6" settings="6">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="RCWSCAS_C64_rcwcomswap" oneofinclass="4" oneof="4" label="RCWSCAS" bitdiffs="A == 0 &amp;&amp; R == 0">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="RCWSCAS"/>
        </docvars>
        <box hibit="23" width="1" name="A">
          <c>0</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>0</c>
        </box>
        <asmtemplate><text>RCWSCAS  </text><a hover="Is the 64-bit name of the general-purpose register to be compared and loaded, encoded in the &quot;Rs&quot; field." link="XsOrXZR__4">&lt;Xs&gt;</a><text>, </text><a hover="Is the 64-bit name of the general-purpose register to be conditionally stored, encoded in the &quot;Rt&quot; field." link="XtOrXZR__10">&lt;Xt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="RCWSCASA_C64_rcwcomswap" oneofinclass="4" oneof="4" label="RCWSCASA" bitdiffs="A == 1 &amp;&amp; R == 0">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="RCWSCASA"/>
        </docvars>
        <box hibit="23" width="1" name="A">
          <c>1</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>0</c>
        </box>
        <asmtemplate><text>RCWSCASA  </text><a hover="Is the 64-bit name of the general-purpose register to be compared and loaded, encoded in the &quot;Rs&quot; field." link="XsOrXZR__4">&lt;Xs&gt;</a><text>, </text><a hover="Is the 64-bit name of the general-purpose register to be conditionally stored, encoded in the &quot;Rt&quot; field." link="XtOrXZR__10">&lt;Xt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="RCWSCASAL_C64_rcwcomswap" oneofinclass="4" oneof="4" label="RCWSCASAL" bitdiffs="A == 1 &amp;&amp; R == 1">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="RCWSCASAL"/>
        </docvars>
        <box hibit="23" width="1" name="A">
          <c>1</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>1</c>
        </box>
        <asmtemplate><text>RCWSCASAL  </text><a hover="Is the 64-bit name of the general-purpose register to be compared and loaded, encoded in the &quot;Rs&quot; field." link="XsOrXZR__4">&lt;Xs&gt;</a><text>, </text><a hover="Is the 64-bit name of the general-purpose register to be conditionally stored, encoded in the &quot;Rt&quot; field." link="XtOrXZR__10">&lt;Xt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <encoding name="RCWSCASL_C64_rcwcomswap" oneofinclass="4" oneof="4" label="RCWSCASL" bitdiffs="A == 0 &amp;&amp; R == 1">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="RCWSCASL"/>
        </docvars>
        <box hibit="23" width="1" name="A">
          <c>0</c>
        </box>
        <box hibit="22" width="1" name="R">
          <c>1</c>
        </box>
        <asmtemplate><text>RCWSCASL  </text><a hover="Is the 64-bit name of the general-purpose register to be compared and loaded, encoded in the &quot;Rs&quot; field." link="XsOrXZR__4">&lt;Xs&gt;</a><text>, </text><a hover="Is the 64-bit name of the general-purpose register to be conditionally stored, encoded in the &quot;Rt&quot; field." link="XtOrXZR__10">&lt;Xt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.ldst.rcwcomswap.RCWSCAS_C64_rcwcomswap" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !IsFeatureImplemented(FEAT_THE) then <a link="func_EndOfDecode_1" file="shared_pseudocode.xml">EndOfDecode</a>(<a link="enum_Decode_UNDEF" file="shared_pseudocode.xml">Decode_UNDEF</a>); end;
let s : integer{} = UInt(Rs);
let t : integer{} = UInt(Rt);
let n : integer{} = UInt(Rn);
let soft : boolean = TRUE;

let acquire : boolean = A == '1' &amp;&amp; s != 31;
let release : boolean = R == '1';
let tagchecked : boolean = n != 31;</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="RCWSCAS_C64_rcwcomswap, RCWSCASA_C64_rcwcomswap, RCWSCASAL_C64_rcwcomswap, RCWSCASL_C64_rcwcomswap" symboldefcount="1">
      <symbol link="XsOrXZR__4">&lt;Xs&gt;</symbol>
      <account encodedin="Rs">
        <intro>
          <para>Is the 64-bit name of the general-purpose register to be compared and loaded, encoded in the &quot;Rs&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RCWSCAS_C64_rcwcomswap, RCWSCASA_C64_rcwcomswap, RCWSCASAL_C64_rcwcomswap, RCWSCASL_C64_rcwcomswap" symboldefcount="1">
      <symbol link="XtOrXZR__10">&lt;Xt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 64-bit name of the general-purpose register to be conditionally stored, encoded in the &quot;Rt&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="RCWSCAS_C64_rcwcomswap, RCWSCASA_C64_rcwcomswap, RCWSCASAL_C64_rcwcomswap, RCWSCASL_C64_rcwcomswap" symboldefcount="1">
      <symbol link="XnSP_option">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A64.ldst.rcwcomswap.RCWSCAS_C64_rcwcomswap" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">if <a link="func_IsD128Enabled_1" file="shared_pseudocode.xml">IsD128Enabled</a>(<a link="global_PSTATE" file="shared_pseudocode.xml">PSTATE</a>.EL) then Undefined(); end;
var address : bits(64);
let newdata : bits(64) = X{}(t);
let compdata : bits(64) = X{}(s);
var readdata : bits(64);
var nzcv : bits(4);

let accdesc : <a link="type_AccessDescriptor" file="shared_pseudocode.xml">AccessDescriptor</a> = <a link="func_CreateAccDescRCW_7" file="shared_pseudocode.xml">CreateAccDescRCW</a>(<a link="enum_MemAtomicOp_CAS" file="shared_pseudocode.xml">MemAtomicOp_CAS</a>, soft, acquire, release,
                                                  tagchecked, t, s);

if n == 31 then
    <a link="func_CheckSPAlignment_0" file="shared_pseudocode.xml">CheckSPAlignment</a>();
    address = <a link="accessor_SP_1" file="shared_pseudocode.xml">SP</a>{64}();
else
    address = <a link="accessor_X_2" file="shared_pseudocode.xml">X</a>{64}(n);
end;

(nzcv, readdata) = <a link="func_MemAtomicRCW_5" file="shared_pseudocode.xml">MemAtomicRCW</a>{64}(address, compdata, newdata, accdesc);

PSTATE.[N,Z,C,V] = nzcv;
<a link="accessor_X_2" file="shared_pseudocode.xml">X</a>{64}(s) = readdata;   // Return the old value when s!=31</pstext></ps>
  </ps_section>
  <timestamp>2026-03-26 20:27:25</timestamp>
  <commit_id>2026-03_rel</commit_id>
</instructionsection>