RCWSET, RCWSETA, RCWSETAL, RCWSETL
Read check write atomic bit set on doubleword in memory
This instruction atomically loads
a 64-bit doubleword from memory, performs a bitwise OR with the value
held in a register on it, and conditionally stores the result back to memory.
Storing of the result back to memory is conditional on RCW Checks. The value initially loaded from memory
is returned in the destination register.
If the RCW Checks fail, the architecture permits writing the value read from the
location to memory. If the write is performed, the read and the write occur
atomically such that no other
modification of the memory location can take place between the read and the write.
This instruction updates the condition flags based on the result of the
RCW Checks.
If the destination register is not XZR, RCWSETA and RCWSETAL load from memory with acquire semantics.
RCWSETL and RCWSETAL store to memory with release semantics.
RCWSET has neither acquire nor release semantics.
This instruction is for performing atomic updates of translation table entries and not
for general use.
0
0
1
1
1
0
0
0
1
1
0
1
1
0
0
0
0
RCWSET <Xs>, <Xt>, [<Xn|SP>]
1
0
RCWSETA <Xs>, <Xt>, [<Xn|SP>]
1
1
RCWSETAL <Xs>, <Xt>, [<Xn|SP>]
0
1
RCWSETL <Xs>, <Xt>, [<Xn|SP>]
if !IsFeatureImplemented(FEAT_THE) then EndOfDecode(Decode_UNDEF); end;
let s : integer{} = UInt(Rs);
let t : integer{} = UInt(Rt);
let n : integer{} = UInt(Rn);
let soft : boolean = FALSE;
let acquire : boolean = A == '1' && t != 31;
let release : boolean = R == '1';
let tagchecked : boolean = n != 31;
<Xs>
Is the 64-bit name of the general-purpose register to be stored, encoded in the "Rs" field.
<Xt>
Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
if IsD128Enabled(PSTATE.EL) then Undefined(); end;
var address : bits(64);
let newdata : bits(64) = X{}(s);
var readdata : bits(64);
var nzcv : bits(4);
let accdesc : AccessDescriptor = CreateAccDescRCW(MemAtomicOp_ORR, soft, acquire, release,
tagchecked, t, s);
if n == 31 then
CheckSPAlignment();
address = SP{64}();
else
address = X{64}(n);
end;
let compdata : bits(64) = ARBITRARY : bits(64); // Irrelevant when not executing CAS
(nzcv, readdata) = MemAtomicRCW{64}(address, compdata, newdata, accdesc);
PSTATE.[N,Z,C,V] = nzcv;
X{64}(t) = readdata; // Return the old value when t!=31
2026-03-26 20:27:25
2026-03_rel