SABD
Signed absolute difference
This instruction subtracts the elements of the vector of the second
source SIMD&FP register from the corresponding elements
of the first source SIMD&FP register, places the absolute values
of the results into a vector,
and writes the vector to the destination
SIMD&FP register.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
0
0
0
1
1
1
0
1
0
1
1
1
0
1
SABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if size == '11' then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);
let esize : integer{} = 8 << UInt(size);
let datasize : integer{} = 64 << UInt(Q);
let elements : integer = datasize DIV esize;
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
Is an arrangement specifier,
size
Q
<T>
00
0
8B
00
1
16B
01
0
4H
01
1
8H
10
0
2S
10
1
4S
11
x
RESERVED
<Vn>
Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>
Is the name of the second SIMD&FP source register, encoded in the "Rm" field.
AArch64_CheckFPAdvSIMDEnabled();
let operand1 : bits(datasize) = V{}(n);
let operand2 : bits(datasize) = V{}(m);
var result : bits(datasize) = Zeros{datasize};
var element1 : integer;
var element2 : integer;
var absdiff : bits(esize);
for e = 0 to elements-1 do
element1 = SInt(operand1[e*:esize]);
element2 = SInt(operand2[e*:esize]);
absdiff = Abs(element1 - element2)[esize-1:0];
result[e*:esize] = result[e*:esize] + absdiff;
end;
V{datasize}(d) = result;
2026-03-26 20:27:25
2026-03_rel