<?xml version="1.0" ?><?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?><!DOCTYPE instructionsection  PUBLIC '-//ARM//DTD instructionsection //EN'  'iform-p.dtd'><!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. --><!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. --><instructionsection id="SABDL_advsimd" title="SABDL, SABDL2 -- A64" type="instruction">
  <docvars>
    <docvar key="advsimd-reguse" value="3reg-diff"/>
    <docvar key="advsimd-type" value="simd"/>
    <docvar key="instr-class" value="advsimd"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="SABDL"/>
  </docvars>
  <heading>SABDL, SABDL2</heading>
  <desc>
    <brief>
      <para>Signed absolute difference long</para>
    </brief>
    <authored>
      <para>This instruction subtracts the vector elements in the lower or upper half
of the second source SIMD&amp;FP register from the corresponding vector elements
of the first source SIMD&amp;FP register, places the absolute value of the results
into a vector, and writes the vector to the destination SIMD&amp;FP register.
The destination vector elements are twice as long as the source vector elements.</para>
      <para>The <instruction>SABDL</instruction> instruction extracts each source vector from
the lower half of each source register.
The <instruction>SABDL2</instruction> instruction extracts each source vector from
the upper half of each source register.</para>
      <para>Depending on the settings in the <register_link id="AArch64-cpacr_el1.xml" state="AArch64">CPACR_EL1</register_link>,
  <register_link id="AArch64-cptr_el2.xml" state="AArch64">CPTR_EL2</register_link>, and <register_link id="AArch64-cptr_el3.xml" state="AArch64">CPTR_EL3</register_link> registers,
  and the current Security state and Exception level,
  an attempt to execute the instruction might be trapped.</para>
    </authored>
  </desc>
  <operationalnotes>
    <operationalnote>
      <operationalnote_content>
        <para>This instruction is a data-independent-time instruction as described in <xref linkend="ARMARM_BEICCDDAB3">About PSTATE.DIT</xref>.</para>
      </operationalnote_content>
    </operationalnote>
  </operationalnotes>
  <alias_list howmany="0"/>
  <classes>
    <iclass name="Three registers, not all the same type" oneof="1" id="iclass_three_registers_not_all_the_same_type" no_encodings="1" isa="A64">
      <docvars>
        <docvar key="advsimd-reguse" value="3reg-diff"/>
        <docvar key="advsimd-type" value="simd"/>
        <docvar key="instr-class" value="advsimd"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="SABDL"/>
      </docvars>
      <iclassintro count="1"/>
      <arch_variants>
        <arch_variant feature="FEAT_AdvSIMD" name="v8Ap0"/>
      </arch_variants>
      <regdiagram form="32" psname="A64.simd_dp.asimddiff.SABDL_asimddiff_L" tworows="1">
        <box hibit="31" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="30" width="1" name="Q" usename="1">
          <c colspan="1"/>
        </box>
        <box hibit="29" name="U" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="28" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="27" width="3" settings="3">
          <c>1</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="24" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="23" width="2" name="size" usename="1">
          <c colspan="2"/>
        </box>
        <box hibit="21" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="20" width="5" name="Rm" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="15" width="2" settings="2">
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="13" name="op" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="12" width="1" settings="1">
          <c>1</c>
        </box>
        <box hibit="11" width="2" settings="2">
          <c>0</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="4" width="5" name="Rd" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="SABDL_asimddiff_L" oneofinclass="1" oneof="1" label="">
        <docvars>
          <docvar key="advsimd-reguse" value="3reg-diff"/>
          <docvar key="advsimd-type" value="simd"/>
          <docvar key="instr-class" value="advsimd"/>
          <docvar key="isa" value="A64"/>
          <docvar key="mnemonic" value="SABDL"/>
        </docvars>
        <asmtemplate><text>SABDL{</text><a hover="Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is " link="s_2_option">2</a><text>}  </text><a hover="Is the name of the SIMD&amp;FP destination register, encoded in the &quot;Rd&quot; field." link="Vd">&lt;Vd&gt;</a><text>.</text><a hover="Is an arrangement specifier, " link="Ta_option__3">&lt;Ta&gt;</a><text>, </text><a hover="Is the name of the first SIMD&amp;FP source register, encoded in the &quot;Rn&quot; field." link="Vn__2">&lt;Vn&gt;</a><text>.</text><a hover="Is an arrangement specifier, " link="Tb_option__3">&lt;Tb&gt;</a><text>, </text><a hover="Is the name of the second SIMD&amp;FP source register, encoded in the &quot;Rm&quot; field." link="Vm">&lt;Vm&gt;</a><text>.</text><a hover="Is an arrangement specifier, " link="Tb_option__3">&lt;Tb&gt;</a></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.simd_dp.asimddiff.SABDL_asimddiff_L" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !IsFeatureImplemented(FEAT_AdvSIMD) then <a link="func_EndOfDecode_1" file="shared_pseudocode.xml">EndOfDecode</a>(<a link="enum_Decode_UNDEF" file="shared_pseudocode.xml">Decode_UNDEF</a>); end;
if size == '11' then <a link="func_EndOfDecode_1" file="shared_pseudocode.xml">EndOfDecode</a>(<a link="enum_Decode_UNDEF" file="shared_pseudocode.xml">Decode_UNDEF</a>); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);

let esize : integer{} = 8 &lt;&lt; UInt(size);
let datasize : integer{} = 64;
let part : integer = UInt(Q);
let elements : integer = datasize DIV esize;</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="SABDL_asimddiff_L" symboldefcount="1">
      <symbol link="s_2_option">2</symbol>
      <definition encodedin="Q">
        <intro>Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">Q</entry>
                <entry class="symbol">2</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">0</entry>
                <entry class="symbol">[absent]</entry>
              </row>
              <row>
                <entry class="bitfield">1</entry>
                <entry class="symbol">[present]</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SABDL_asimddiff_L" symboldefcount="1">
      <symbol link="Vd">&lt;Vd&gt;</symbol>
      <account encodedin="Rd">
        <intro>
          <para>Is the name of the SIMD&amp;FP destination register, encoded in the &quot;Rd&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SABDL_asimddiff_L" symboldefcount="1">
      <symbol link="Ta_option__3">&lt;Ta&gt;</symbol>
      <definition encodedin="size">
        <intro>Is an arrangement specifier, </intro>
        <table class="valuetable">
          <tgroup cols="2">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="symbol">&lt;Ta&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="symbol">8H</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="symbol">4S</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="symbol">2D</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SABDL_asimddiff_L" symboldefcount="1">
      <symbol link="Vn__2">&lt;Vn&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the name of the first SIMD&amp;FP source register, encoded in the &quot;Rn&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="SABDL_asimddiff_L" symboldefcount="1">
      <symbol link="Tb_option__3">&lt;Tb&gt;</symbol>
      <definition encodedin="(size :: Q)">
        <intro>Is an arrangement specifier, </intro>
        <table class="valuetable">
          <tgroup cols="3">
            <thead>
              <row>
                <entry class="bitfield">size</entry>
                <entry class="bitfield">Q</entry>
                <entry class="symbol">&lt;Tb&gt;</entry>
              </row>
            </thead>
            <tbody>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">8B</entry>
              </row>
              <row>
                <entry class="bitfield">00</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">16B</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">4H</entry>
              </row>
              <row>
                <entry class="bitfield">01</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">8H</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="bitfield">0</entry>
                <entry class="symbol">2S</entry>
              </row>
              <row>
                <entry class="bitfield">10</entry>
                <entry class="bitfield">1</entry>
                <entry class="symbol">4S</entry>
              </row>
              <row>
                <entry class="bitfield">11</entry>
                <entry class="bitfield">x</entry>
                <entry class="symbol">RESERVED</entry>
              </row>
            </tbody>
          </tgroup>
        </table>
      </definition>
    </explanation>
    <explanation enclist="SABDL_asimddiff_L" symboldefcount="1">
      <symbol link="Vm">&lt;Vm&gt;</symbol>
      <account encodedin="Rm">
        <intro>
          <para>Is the name of the second SIMD&amp;FP source register, encoded in the &quot;Rm&quot; field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A64.simd_dp.asimddiff.SABDL_asimddiff_L" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="func_AArch64_CheckFPAdvSIMDEnabled_0" file="shared_pseudocode.xml">AArch64_CheckFPAdvSIMDEnabled</a>();
let operand1 : bits(datasize) = Vpart{}(n, part);
let operand2 : bits(datasize) = Vpart{}(m, part);
var result : bits(2*datasize) = Zeros{2*datasize};
var element1 : integer;
var element2 : integer;
var absdiff : bits(2*esize);

for e = 0 to elements-1 do
    element1 = SInt(operand1[e*:esize]);
    element2 = SInt(operand2[e*:esize]);
    absdiff = Abs(element1-element2)[2*esize-1:0];
    result[e*:(2*esize)] = result[e*:(2*esize)] + absdiff;
end;
<a link="accessor_V_2" file="shared_pseudocode.xml">V</a>{2*datasize}(d) = result;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-26 20:27:25</timestamp>
  <commit_id>2026-03_rel</commit_id>
</instructionsection>