SLI
Shift left and insert (immediate)
This instruction reads each vector element in the
source SIMD&FP register,
left shifts each vector element by an immediate value, and
inserts the result into the corresponding vector element
in the destination SIMD&FP register such that the new zero bits created
by the shift are not inserted but retain their existing value.
Bits shifted out of the left of each vector element in the
source register are lost.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
It has encodings from 2 classes:
Scalar
and
Vector
0
1
1
1
1
1
1
1
0
1
x
x
x
0
1
0
1
0
1
SLI D<d>, D<n>, #<shift>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if immh[3] != '1' then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let esize : integer{} = 8 << 3;
let datasize : integer{} = esize;
let elements : integer = 1;
let shift : integer = UInt(immh::immb) - esize;
0
1
0
1
1
1
1
0
!= 0000
0
1
0
1
0
1
SLI <Vd>.<T>, <Vn>.<T>, #<shift>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if immh[3]::Q == '10' then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let esize : integer{} = 8 << HighestSetBitNZ(immh);
let datasize : integer{} = 64 << UInt(Q);
let elements : integer = datasize DIV esize;
let shift : integer = UInt(immh::immb) - esize;
<d>
Is the number of the SIMD&FP destination register, encoded in the "Rd" field.
<n>
Is the number of the SIMD&FP source register, encoded in the "Rn" field.
<shift>
For the "Scalar" variant: is the left shift amount, in the range 0 to 63, encoded as UInt("immh:immb") - 64.
<shift>
For the "Vector" variant: is the left shift amount, in the range 0 to the element width in bits minus 1,
immh
<shift>
0001
UInt(immh :: immb) - 8
001x
UInt(immh :: immb) - 16
01xx
UInt(immh :: immb) - 32
1xxx
UInt(immh :: immb) - 64
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<T>
Is an arrangement specifier,
immh
Q
<T>
0001
0
8B
0001
1
16B
001x
0
4H
001x
1
8H
01xx
0
2S
01xx
1
4S
1xxx
0
RESERVED
1xxx
1
2D
<Vn>
Is the name of the SIMD&FP source register, encoded in the "Rn" field.
AArch64_CheckFPAdvSIMDEnabled();
let operand : bits(datasize) = V{}(n);
let operand2 : bits(datasize) = V{}(d);
let mask : bits(esize) = LSL(Ones{esize}, shift);
var result : bits(datasize);
var shifted : bits(esize);
for e = 0 to elements-1 do
shifted = LSL(operand[e*:esize], shift);
result[e*:esize] = (operand2[e*:esize] AND NOT(mask)) OR shifted;
end;
V{datasize}(d) = result;
2026-03-26 20:27:25
2026-03_rel