SMOV
Signed move vector element to general-purpose register
This instruction reads the signed integer from the
source SIMD&FP register,
sign-extends it to form a 32-bit or 64-bit value, and writes the result to
destination general-purpose register.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
0
0
0
1
1
1
0
0
0
0
0
0
1
0
1
1
0
SMOV <Wd>, <Vn>.<Ts>[<index>]
1
SMOV <Xd>, <Vn>.<Ts>[<index>]
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if imm5 == 'xx000' then EndOfDecode(Decode_UNDEF); end;
let size : integer{} = LowestSetBitNZ(imm5[2:0]);
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let esize : integer{} = 8 << size;
let datasize : integer{} = 32 << UInt(Q);
if datasize <= esize then EndOfDecode(Decode_UNDEF); end;
let index : integer = UInt(imm5[4:size+1]);
let idxdsize : integer{} = 64 << UInt(imm5[4]);
<Wd>
Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.
<Vn>
Is the name of the SIMD&FP source register, encoded in the "Rn" field.
<Ts>
For the "32-bit" variant: is an element size specifier,
imm5
<Ts>
xxx00
RESERVED
xxxx1
B
xxx10
H
<Ts>
For the "64-bit" variant: is an element size specifier,
imm5
<Ts>
xx000
RESERVED
xxxx1
B
xxx10
H
xx100
S
<index>
For the "32-bit" variant: is the element index
imm5
<index>
xxx00
RESERVED
xxxx1
UInt(imm5[4:1])
xxx10
UInt(imm5[4:2])
<index>
For the "64-bit" variant: is the element index
imm5
<index>
xx000
RESERVED
xxxx1
UInt(imm5[4:1])
xxx10
UInt(imm5[4:2])
xx100
UInt(imm5[4:3])
<Xd>
Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.
if index == 0 then
AArch64_CheckFPEnabled();
else
AArch64_CheckFPAdvSIMDEnabled();
end;
let operand : bits(idxdsize) = V{}(n);
X{datasize}(d) = SignExtend{datasize}(operand[index*:esize]);
2026-03-26 20:27:25
2026-03_rel