STILP
Store-release ordered pair of registers
This instruction calculates an address from a base register value and an optional offset,
and stores two 32-bit words or two
64-bit doublewords to the calculated address, from two registers.
For information on single-copy atomicity and alignment requirements,
see Requirements for single-copy atomicity and
Alignment of data accesses.
The instruction also has memory ordering
semantics, as described in
Load-Acquire, Load-AcquirePC, and Store-Release, with the additional requirement that:
When using the pre-index addressing mode, the Memory effects associated with Xt2/Wt2 are Ordered-before
the Memory effects associated with Xt1/Wt1.
For all other addressing modes, the Memory effects associated with Xt1/Wt1 are Ordered-before the Memory
effects associated with Xt2/Wt2.
For information about addressing modes, see Load/Store addressing modes.
STILP has the same CONSTRAINED UNPREDICTABLE behavior as STP. For information about this CONSTRAINED UNPREDICTABLE behavior, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly STP and STILP.
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
1
x
0
1
1
0
0
1
0
0
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x
1
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STILP <Wt1>, <Wt2>, [<Xn|SP>, #-8]!
0
1
STILP <Wt1>, <Wt2>, [<Xn|SP>]
1
0
STILP <Xt1>, <Xt2>, [<Xn|SP>, #-16]!
1
1
STILP <Xt1>, <Xt2>, [<Xn|SP>]
if !IsFeatureImplemented(FEAT_LRCPC3) then EndOfDecode(Decode_UNDEF); end;
let ispair : boolean = TRUE;
let wback : boolean = opc2[0] == '0';
<Wt1>
Is the 32-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
<Wt2>
Is the 32-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<Xt1>
Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.
<Xt2>
Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.
let t : integer{} = UInt(Rt);
let t2 : integer{} = UInt(Rt2);
let n : integer{} = UInt(Rn);
let scale : integer{} = 2 + UInt(size[0]);
let datasize : integer{} = 8 << scale;
let offset : integer = if opc2[0] == '0' then -1 * (2 << scale) else 0;
let acqrel : boolean = FALSE;
let tagchecked : boolean = wback || n != 31;
var rt_unknown : boolean = FALSE;
if wback && (t == n || t2 == n) && n != 31 then
let c : Constraint = ConstrainUnpredictable(Unpredictable_WBOVERLAPST);
assert c IN {Constraint_NONE, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_NONE => rt_unknown = FALSE; // value stored is pre-writeback
when Constraint_UNKNOWN => rt_unknown = TRUE; // value stored is UNKNOWN
when Constraint_UNDEF => EndOfDecode(Decode_UNDEF);
when Constraint_NOP => EndOfDecode(Decode_NOP);
end;
end;
var address : bits(64);
var data1 : bits(datasize);
var data2 : bits(datasize);
let dbytes : integer{} = datasize DIV 8;
var accdesc : AccessDescriptor = CreateAccDescAcqRel(MemOp_STORE, tagchecked,
ispair, acqrel, t, t2);
if n == 31 then
CheckSPAlignment();
address = SP{64}();
else
address = X{64}(n);
end;
address = AddressAdd(address, offset, accdesc);
if rt_unknown && t == n then
data1 = ARBITRARY : bits(datasize);
else
data1 = X{datasize}(t);
end;
if rt_unknown && t2 == n then
data2 = ARBITRARY : bits(datasize);
else
data2 = X{datasize}(t2);
end;
var full_data : bits(2*datasize);
if BigEndian(accdesc.acctype) then
full_data = data1::data2;
else
full_data = data2::data1;
end;
accdesc.highestaddressfirst = offset < 0;
Mem{2*datasize}(address, accdesc) = full_data;
if wback then
if n == 31 then
SP{64}() = address;
else
X{64}(n) = address;
end;
end;
2026-03-26 20:27:25
2026-03_rel