<?xml version="1.0" ?><?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?><!DOCTYPE instructionsection  PUBLIC '-//ARM//DTD instructionsection //EN'  'iform-p.dtd'><!-- Copyright (c) 2010-2026 Arm Limited or its affiliates. All rights reserved. --><!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. --><instructionsection id="STLR" title="STLR -- A64" type="instruction">
  <docvars>
    <docvar key="instr-class" value="general"/>
    <docvar key="isa" value="A64"/>
    <docvar key="mnemonic" value="STLR"/>
  </docvars>
  <heading>STLR</heading>
  <desc>
    <brief>
      <para>Store-release register</para>
    </brief>
    <authored>
      <para>This instruction stores a 32-bit word or
a 64-bit doubleword to a memory location,
from a register.
The instruction also has memory ordering
semantics as described in
<xref linkend="ARMARM_BEIHCHEF">Load-Acquire, Store-Release</xref>.
For information about addressing modes, see
<xref linkend="ARMARM_CHDIIIBB">Load/Store addressing modes</xref>.</para>
    </authored>
  </desc>
  <operationalnotes>
    <operationalnote>
      <operationalnote_content>
        <para>This instruction is a data-independent-time instruction as described in <xref linkend="ARMARM_BEICCDDAB3">About PSTATE.DIT</xref>.</para>
      </operationalnote_content>
    </operationalnote>
  </operationalnotes>
  <alias_list howmany="0"/>
  <classes>
    <classesintro count="2">
      <txt>It has encodings from 2 classes:</txt>
      <a href="#iclass_no_offset">No offset</a>
      <txt> and </txt>
      <a href="#iclass_pre_index">Pre-index</a>
    </classesintro>
    <iclass name="No offset" oneof="2" id="iclass_no_offset" no_encodings="2" isa="A64">
      <docvars>
        <docvar key="address-form" value="base-register"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="STLR"/>
      </docvars>
      <iclassintro count="2"/>
      <regdiagram form="32" psname="A64.ldst.ldstord.STLR_SL32_ldstord" tworows="1">
        <box hibit="31" width="2" name="size" usename="1" settings="1" psbits="xx">
          <c>1</c>
          <c>x</c>
        </box>
        <box hibit="29" width="7" settings="7">
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
        </box>
        <box hibit="22" name="L" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="21" width="1" settings="1">
          <c>0</c>
        </box>
        <box hibit="20" width="5" name="Rs" usename="1" settings="5" psbits="xxxxx">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="15" name="o0" usename="1" settings="1" psbits="x">
          <c>1</c>
        </box>
        <box hibit="14" width="5" name="Rt2" usename="1" settings="5" psbits="xxxxx">
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
          <c>(1)</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="STLR_SL32_ldstord" oneofinclass="2" oneof="4" label="32-bit" bitdiffs="size == 10">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="address-form" value="base-register"/>
          <docvar key="address-form-reg-type" value="base-register-32-reg"/>
          <docvar key="atomic-ops" value="STLR-32-reg"/>
          <docvar key="reg-type" value="32-reg"/>
          <docvar key="mnemonic" value="STLR"/>
        </docvars>
        <box hibit="31" width="2" name="size">
          <c/>
          <c>0</c>
        </box>
        <asmtemplate><text>STLR  </text><a hover="Is the 32-bit name of the general-purpose register to be transferred, encoded in the &quot;Rt&quot; field." link="WtOrWZR__4">&lt;Wt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>{, #0}]</text></asmtemplate>
      </encoding>
      <encoding name="STLR_SL64_ldstord" oneofinclass="2" oneof="4" label="64-bit" bitdiffs="size == 11">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="address-form" value="base-register"/>
          <docvar key="address-form-reg-type" value="base-register-64-reg"/>
          <docvar key="atomic-ops" value="STLR-64-reg"/>
          <docvar key="reg-type" value="64-reg"/>
          <docvar key="mnemonic" value="STLR"/>
        </docvars>
        <box hibit="31" width="2" name="size">
          <c/>
          <c>1</c>
        </box>
        <asmtemplate><text>STLR  </text><a hover="Is the 64-bit name of the general-purpose register to be transferred, encoded in the &quot;Rt&quot; field." link="XtOrXZR__11">&lt;Xt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>{, #0}]</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.ldst.ldstord.STLR_SL32_ldstord" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">let t : integer{} = UInt(Rt);
let n : integer{} = UInt(Rn);
let wback : boolean = FALSE;
let offset : integer = 0;
let rt_unknown : boolean = FALSE;

let elsize : integer{} = 8 &lt;&lt; UInt(size);
let datasize : integer{} = elsize;
let acquire : boolean = FALSE;
let tagchecked : boolean = n != 31;</pstext></ps>
      </ps_section>
    </iclass>
    <iclass name="Pre-index" oneof="2" id="iclass_pre_index" no_encodings="2" isa="A64">
      <docvars>
        <docvar key="address-form" value="pre-indexed"/>
        <docvar key="instr-class" value="general"/>
        <docvar key="isa" value="A64"/>
        <docvar key="mnemonic" value="STLR"/>
      </docvars>
      <iclassintro count="2"/>
      <arch_variants>
        <arch_variant feature="FEAT_LRCPC3" name="v8Ap9"/>
      </arch_variants>
      <regdiagram form="32" psname="A64.ldst.ldapstl_writeback.STLR_32S_ldapstl_writeback" tworows="1">
        <box hibit="31" width="2" name="size" usename="1" settings="1" psbits="xx">
          <c>1</c>
          <c>x</c>
        </box>
        <box hibit="29" width="7" settings="7">
          <c>0</c>
          <c>1</c>
          <c>1</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>1</c>
        </box>
        <box hibit="22" name="L" usename="1" settings="1" psbits="x">
          <c>0</c>
        </box>
        <box hibit="21" width="12" settings="12">
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>0</c>
          <c>1</c>
          <c>0</c>
        </box>
        <box hibit="9" width="5" name="Rn" usename="1">
          <c colspan="5"/>
        </box>
        <box hibit="4" width="5" name="Rt" usename="1">
          <c colspan="5"/>
        </box>
      </regdiagram>
      <encoding name="STLR_32S_ldapstl_writeback" oneofinclass="2" oneof="4" label="32-bit" bitdiffs="size == 10">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="address-form" value="pre-indexed"/>
          <docvar key="address-form-reg-type" value="pre-indexed-32-reg"/>
          <docvar key="atomic-ops" value="STLR-32-reg"/>
          <docvar key="reg-type" value="32-reg"/>
          <docvar key="mnemonic" value="STLR"/>
        </docvars>
        <box hibit="31" width="2" name="size">
          <c/>
          <c>0</c>
        </box>
        <asmtemplate><text>STLR  </text><a hover="Is the 32-bit name of the general-purpose register to be transferred, encoded in the &quot;Rt&quot; field." link="WtOrWZR__4">&lt;Wt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>, #-4]!</text></asmtemplate>
      </encoding>
      <encoding name="STLR_64S_ldapstl_writeback" oneofinclass="2" oneof="4" label="64-bit" bitdiffs="size == 11">
        <docvars>
          <docvar key="instr-class" value="general"/>
          <docvar key="isa" value="A64"/>
          <docvar key="address-form" value="pre-indexed"/>
          <docvar key="address-form-reg-type" value="pre-indexed-64-reg"/>
          <docvar key="atomic-ops" value="STLR-64-reg"/>
          <docvar key="reg-type" value="64-reg"/>
          <docvar key="mnemonic" value="STLR"/>
        </docvars>
        <box hibit="31" width="2" name="size">
          <c/>
          <c>1</c>
        </box>
        <asmtemplate><text>STLR  </text><a hover="Is the 64-bit name of the general-purpose register to be transferred, encoded in the &quot;Rt&quot; field." link="XtOrXZR__11">&lt;Xt&gt;</a><text>, [</text><a hover="Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field." link="XnSP_option">&lt;Xn|SP&gt;</a><text>, #-8]!</text></asmtemplate>
      </encoding>
      <ps_section howmany="1">
        <ps name="A64.ldst.ldapstl_writeback.STLR_32S_ldapstl_writeback" sections="1" secttype="noheading">
          <pstext mayhavelinks="1" section="Decode" rep_section="decode">if !IsFeatureImplemented(FEAT_LRCPC3) then <a link="func_EndOfDecode_1" file="shared_pseudocode.xml">EndOfDecode</a>(<a link="enum_Decode_UNDEF" file="shared_pseudocode.xml">Decode_UNDEF</a>); end;
let wback : boolean = TRUE;

let t : integer{} = UInt(Rt);
let n : integer{} = UInt(Rn);

let datasize : integer{} = 8 &lt;&lt; UInt(size);
let offset : integer = -1 * (1 &lt;&lt; UInt(size));
let acquire : boolean = FALSE;
let tagchecked : boolean = TRUE;

var rt_unknown : boolean = FALSE;

if n == t &amp;&amp; n != 31 then
    let c : <a link="type_Constraint" file="shared_pseudocode.xml">Constraint</a> = ConstrainUnpredictable(<a link="enum_Unpredictable_WBOVERLAPST" file="shared_pseudocode.xml">Unpredictable_WBOVERLAPST</a>);
    assert c IN {<a link="enum_Constraint_NONE" file="shared_pseudocode.xml">Constraint_NONE</a>, <a link="enum_Constraint_UNKNOWN" file="shared_pseudocode.xml">Constraint_UNKNOWN</a>, <a link="enum_Constraint_UNDEF" file="shared_pseudocode.xml">Constraint_UNDEF</a>, <a link="enum_Constraint_NOP" file="shared_pseudocode.xml">Constraint_NOP</a>};
    case c of
        when <a link="enum_Constraint_NONE" file="shared_pseudocode.xml">Constraint_NONE</a> =&gt;    rt_unknown = FALSE;   // value stored is original value
        when <a link="enum_Constraint_UNKNOWN" file="shared_pseudocode.xml">Constraint_UNKNOWN</a> =&gt; rt_unknown = TRUE;    // value stored is UNKNOWN
        when <a link="enum_Constraint_UNDEF" file="shared_pseudocode.xml">Constraint_UNDEF</a> =&gt;   <a link="func_EndOfDecode_1" file="shared_pseudocode.xml">EndOfDecode</a>(<a link="enum_Decode_UNDEF" file="shared_pseudocode.xml">Decode_UNDEF</a>);
        when <a link="enum_Constraint_NOP" file="shared_pseudocode.xml">Constraint_NOP</a> =&gt;     <a link="func_EndOfDecode_1" file="shared_pseudocode.xml">EndOfDecode</a>(<a link="enum_Decode_NOP" file="shared_pseudocode.xml">Decode_NOP</a>);
    end;
end;</pstext></ps>
      </ps_section>
    </iclass>
  </classes>
  <explanations scope="all">
    <explanation enclist="STLR_SL32_ldstord, STLR_32S_ldapstl_writeback" symboldefcount="1">
      <symbol link="WtOrWZR__4">&lt;Wt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 32-bit name of the general-purpose register to be transferred, encoded in the &quot;Rt&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLR_SL32_ldstord, STLR_SL64_ldstord, STLR_32S_ldapstl_writeback, STLR_64S_ldapstl_writeback" symboldefcount="1">
      <symbol link="XnSP_option">&lt;Xn|SP&gt;</symbol>
      <account encodedin="Rn">
        <intro>
          <para>Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the &quot;Rn&quot; field.</para>
        </intro>
      </account>
    </explanation>
    <explanation enclist="STLR_SL64_ldstord, STLR_64S_ldapstl_writeback" symboldefcount="1">
      <symbol link="XtOrXZR__11">&lt;Xt&gt;</symbol>
      <account encodedin="Rt">
        <intro>
          <para>Is the 64-bit name of the general-purpose register to be transferred, encoded in the &quot;Rt&quot; field.</para>
        </intro>
      </account>
    </explanation>
  </explanations>
  <ps_section howmany="1">
    <ps name="A64.ldst.ldstord.STLR_SL32_ldstord" sections="1" secttype="Operation">
      <pstext mayhavelinks="1" section="Execute" rep_section="execute">var address : bits(64);
let dbytes : integer{} = datasize DIV 8;

let accdesc : <a link="type_AccessDescriptor" file="shared_pseudocode.xml">AccessDescriptor</a> = <a link="func_CreateAccDescAcqRel_4" file="shared_pseudocode.xml">CreateAccDescAcqRel</a>(<a link="enum_MemOp_STORE" file="shared_pseudocode.xml">MemOp_STORE</a>, tagchecked, acquire, t);

if n == 31 then
    <a link="func_CheckSPAlignment_0" file="shared_pseudocode.xml">CheckSPAlignment</a>();
    address = <a link="accessor_SP_1" file="shared_pseudocode.xml">SP</a>{64}();
else
    address = <a link="accessor_X_2" file="shared_pseudocode.xml">X</a>{64}(n);
end;

address = <a link="func_AddressAdd_3" file="shared_pseudocode.xml">AddressAdd</a>(address, offset, accdesc);
var data : bits(datasize);
if rt_unknown then
    data = ARBITRARY : bits(datasize);
else
    data = <a link="accessor_X_2" file="shared_pseudocode.xml">X</a>{datasize}(t);
end;
<a link="accessor_Mem_3" file="shared_pseudocode.xml">Mem</a>{datasize}(address, accdesc) = data;
if wback then
    if n == 31 then
        <a link="accessor_SP_1" file="shared_pseudocode.xml">SP</a>{64}() = address;
    else
        <a link="accessor_X_2" file="shared_pseudocode.xml">X</a>{64}(n) = address;
    end;
end;</pstext></ps>
  </ps_section>
  <timestamp>2026-03-26 20:27:25</timestamp>
  <commit_id>2026-03_rel</commit_id>
</instructionsection>