STTXR
Store unprivileged exclusive register
This instruction
stores a 32-bit word or a 64-bit doubleword from a register to
memory if the PE has
exclusive access to the memory address, and returns a status
value of 0 if the
store was successful, or of 1 if no store was performed.
See
Synchronization and semaphores.
Explicit Memory effects produced by the instruction behave as if the instruction was
executed at EL0 if the Effective value of
PSTATE.UAO is 0 and either:
The instruction is executed at EL1.
The instruction is executed at EL2 when the Effective value
of HCR_EL2().{E2H, TGE} is '11'.
Otherwise, the Explicit Memory effects operate with the restrictions determined by
the Exception level at which the instruction is executed.
For the purposes of the Exclusives monitors, and the forward progress guarantees for
Load-Exclusive and Store-Exclusive loops, STTXR is
equivalent to STXR.
For information about addressing modes, see
Load/Store addressing modes.
STTXR has the same CONSTRAINED UNPREDICTABLE behavior as STXR. See Architectural Constraints on UNPREDICTABLE behaviors, and particularly STXR.
Aborts and alignment
If a synchronous Data Abort exception is generated by the execution of this instruction:
Memory is not updated.
<Ws> is not updated.
Accessing an address that is not aligned to the size of the data being accessed causes an
Alignment fault Data Abort exception to be generated, subject to the following rules:
If AArch64_ExclusiveMonitorsPass() returns TRUE, the exception
is generated.
Otherwise, it is IMPLEMENTATION DEFINED whether the exception is generated.
If AArch64_ExclusiveMonitorsPass() returns FALSE and the
memory address, if accessed, would generate a synchronous Data Abort exception, it is
IMPLEMENTATION DEFINED whether the exception is generated.
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
1
0
0
1
0
0
1
0
0
0
0
(1)
(1)
(1)
(1)
(1)
0
STTXR <Ws>, <Wt>, [<Xn|SP>{, #0}]
1
STTXR <Ws>, <Xt>, [<Xn|SP>{, #0}]
if !IsFeatureImplemented(FEAT_LSUI) then EndOfDecode(Decode_UNDEF); end;
let s : integer{} = UInt(Rs);
let t : integer{} = UInt(Rt);
let n : integer{} = UInt(Rn);
let elsize : integer{} = 32 << UInt(sz);
let acqrel : boolean = FALSE;
let tagchecked : boolean = n != 31;
var rt_unknown : boolean = FALSE;
var rn_unknown : boolean = FALSE;
if s == t then
let c : Constraint = ConstrainUnpredictable(Unpredictable_DATAOVERLAP);
assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_UNKNOWN => rt_unknown = TRUE; // store UNKNOWN value
when Constraint_UNDEF => EndOfDecode(Decode_UNDEF);
when Constraint_NOP => EndOfDecode(Decode_NOP);
end;
end;
if s == n && n != 31 then
let c : Constraint = ConstrainUnpredictable(Unpredictable_BASEOVERLAP);
assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP};
case c of
when Constraint_UNKNOWN => rn_unknown = TRUE; // address is UNKNOWN
when Constraint_UNDEF => EndOfDecode(Decode_UNDEF);
when Constraint_NOP => EndOfDecode(Decode_NOP);
end;
end;
<Ws>
Is the 32-bit name of the general-purpose register into which the status result of the store exclusive is written, encoded in the "Rs" field. The value returned is:
0
If the operation updates memory.
1
If the operation fails to update memory.
<Wt>
Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<Xt>
Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.
var address : bits(64);
var data : bits(elsize);
let dbytes : integer{} = elsize DIV 8;
let privileged : boolean = AArch64_IsUnprivAccessPriv();
let accdesc : AccessDescriptor = CreateAccDescExLDST(MemOp_STORE, acqrel,
tagchecked, privileged, t);
if n == 31 then
CheckSPAlignment();
address = SP{64}();
elsif rn_unknown then
address = ARBITRARY : bits(64);
else
address = X{64}(n);
end;
if rt_unknown then
data = ARBITRARY : bits(elsize);
else
data = X{elsize}(t);
end;
var status : bit = '1';
// Check whether the Exclusives monitors are set to include the
// physical memory locations corresponding to virtual address
// range [address, address+dbytes-1].
// If AArch64_ExclusiveMonitorsPass() returns FALSE and the memory address,
// if accessed, would generate a synchronous Data Abort exception, it is
// IMPLEMENTATION DEFINED whether the exception is generated.
// It is a limitation of this model that synchronous Data Aborts are never
// generated in this case, as Mem is not called.
// If FEAT_SPE is implemented, it is also IMPLEMENTATION DEFINED whether or not the
// physical address packet is output when permitted and when
// AArch64_ExclusiveMonitorPass() returns FALSE for a Store Exclusive instruction.
// This behavior is not reflected here due to the previously stated limitation.
if AArch64_ExclusiveMonitorsPass(address, dbytes, accdesc) then
// This atomic write will be rejected if it does not refer
// to the same physical locations after address translation.
Mem{elsize}(address, accdesc) = data;
status = ExclusiveMonitorsStatus();
end;
X{32}(s) = ZeroExtend{32}(status);
2026-03-26 20:27:25
2026-03_rel