SWPT, SWPTA, SWPTAL, SWPTL
Swap unprivileged
This instruction atomically loads a 32-bit word or
64-bit doubleword from a memory location,
and stores the value held in a register back to the same memory location.
The value initially loaded from memory is returned in the destination register.
If the destination register is not one of WZR or
XZR, SWPTA and SWPTAL load from memory with acquire semantics.
SWPTL and SWPTAL store to memory with release semantics.
SWPT has neither acquire nor release semantics.
For more information about memory ordering semantics, see Load-Acquire, Store-Release.
For information about addressing modes, see
Load/Store addressing modes.
Explicit Memory effects produced by the instruction behave as if the instruction was
executed at EL0 if the Effective value of
PSTATE.UAO is 0 and either:
The instruction is executed at EL1.
The instruction is executed at EL2 when the Effective value
of HCR_EL2().{E2H, TGE} is '11'.
Otherwise, the Explicit Memory effects operate with the restrictions determined by
the Exception level at which the instruction is executed.
0
0
1
1
0
0
1
1
1
0
0
0
0
1
0
0
0
SWPT <Ws>, <Wt>, [<Xn|SP>]
0
1
0
SWPTA <Ws>, <Wt>, [<Xn|SP>]
0
1
1
SWPTAL <Ws>, <Wt>, [<Xn|SP>]
0
0
1
SWPTL <Ws>, <Wt>, [<Xn|SP>]
1
0
0
SWPT <Xs>, <Xt>, [<Xn|SP>]
1
1
0
SWPTA <Xs>, <Xt>, [<Xn|SP>]
1
1
1
SWPTAL <Xs>, <Xt>, [<Xn|SP>]
1
0
1
SWPTL <Xs>, <Xt>, [<Xn|SP>]
if !IsFeatureImplemented(FEAT_LSUI) then EndOfDecode(Decode_UNDEF); end;
let s : integer{} = UInt(Rs);
let t : integer{} = UInt(Rt);
let n : integer{} = UInt(Rn);
let datasize : integer{} = 32 << UInt(sz);
let regsize : integer{} = if datasize == 64 then 64 else 32;
let acquire : boolean = A == '1' && Rt != '11111';
let release : boolean = R == '1';
let tagchecked : boolean = n != 31;
<Ws>
Is the 32-bit name of the general-purpose register to be stored, encoded in the "Rs" field.
<Wt>
Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
<Xn|SP>
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.
<Xs>
Is the 64-bit name of the general-purpose register to be stored, encoded in the "Rs" field.
<Xt>
Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.
var address : bits(64);
var data : bits(datasize);
var store_value : bits(datasize);
let privileged : boolean = AArch64_IsUnprivAccessPriv();
let accdesc : AccessDescriptor = CreateAccDescAtomicOp(MemAtomicOp_SWP, acquire, release,
tagchecked, privileged, t, s);
if n == 31 then
CheckSPAlignment();
address = SP{64}();
else
address = X{64}(n);
end;
store_value = X{datasize}(s);
let comparevalue : bits(datasize) = ARBITRARY : bits(datasize); // Irrelevant when not executing CAS
data = MemAtomic{datasize}(address, comparevalue, store_value, accdesc);
X{regsize}(t) = ZeroExtend{regsize}(data);
2026-03-26 20:27:25
2026-03_rel