TSB Trace synchronization barrier This instruction is a barrier that synchronizes the trace operations of instructions, see Trace Synchronization Barrier (TSB). If FEAT_TRF is not implemented, this instruction executes as a NOP. 1 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 1 0 1 1 1 1 1 TSB CSYNC if !IsFeatureImplemented(FEAT_TRF) then EndOfDecode(Decode_NOP); end; if IsFeatureImplemented(FEAT_FGT2) && IsFeatureImplemented(FEAT_TRBEv1p1) then let trap_to_el2 : boolean = (PSTATE.EL IN {EL0, EL1} && EL2Enabled() && !IsInHost() && (!HaveEL(EL3) || SCR_EL3().FGTEn2 == '1') && HFGITR2_EL2().TSBCSYNC == '1'); if trap_to_el2 then let target_el : bits(2) = EL2; let iss : bits(25) = 0x4[24:0]; AArch64_OtherInstrTrap(target_el, iss); end; end; TraceSynchronizationBarrier(); 2026-03-26 20:27:25 2026-03_rel