UADDW, UADDW2
Unsigned add wide
This instruction adds the vector elements of the
first source SIMD&FP register to the corresponding vector elements
in the lower or upper half of the second
source SIMD&FP register,
places the result in a vector,
and writes the vector to the SIMD&FP destination register.
The vector elements of the destination register and the first source
register are twice as long as the vector elements of the second source register.
All the values in this instruction are unsigned integer values.
The UADDW instruction extracts
vector elements
from the lower half
of the second source register. The UADDW2 instruction extracts
vector elements from the upper half
of the second source register.
Depending on the settings in the CPACR_EL1,
CPTR_EL2, and CPTR_EL3 registers,
and the current Security state and Exception level,
an attempt to execute the instruction might be trapped.
This instruction is a data-independent-time instruction as described in About PSTATE.DIT.
0
1
0
1
1
1
0
1
0
0
0
1
0
0
UADDW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>
if !IsFeatureImplemented(FEAT_AdvSIMD) then EndOfDecode(Decode_UNDEF); end;
if size == '11' then EndOfDecode(Decode_UNDEF); end;
let d : integer{} = UInt(Rd);
let n : integer{} = UInt(Rn);
let m : integer{} = UInt(Rm);
let esize : integer{} = 8 << UInt(size);
let datasize : integer{} = 64;
let part : integer = UInt(Q);
let elements : integer = datasize DIV esize;
2
Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is
Q
2
0
[absent]
1
[present]
<Vd>
Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<Ta>
Is an arrangement specifier,
size
<Ta>
00
8H
01
4S
10
2D
11
RESERVED
<Vn>
Is the name of the first SIMD&FP source register, encoded in the "Rn" field.
<Vm>
Is the name of the second SIMD&FP source register, encoded in the "Rm" field.
<Tb>
Is an arrangement specifier,
size
Q
<Tb>
00
0
8B
00
1
16B
01
0
4H
01
1
8H
10
0
2S
10
1
4S
11
x
RESERVED
AArch64_CheckFPAdvSIMDEnabled();
let operand1 : bits(2*datasize) = V{}(n);
let operand2 : bits(datasize) = Vpart{}(m, part);
var result : bits(2*datasize);
var element1 : integer;
var element2 : integer;
var sum : integer;
for e = 0 to elements-1 do
element1 = UInt(operand1[e*:(2*esize)]);
element2 = UInt(operand2[e*:esize]);
sum = element1 + element2;
result[e*:(2*esize)] = sum[2*esize-1:0];
end;
V{2*datasize}(d) = result;
2026-03-26 20:27:25
2026-03_rel