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LDAPR -- A64

LDAPR

Load-acquire RCpc register

This instruction derives an address from a base register value, loads a 32-bit word or 64-bit doubleword from the derived address in memory, and writes it to a register.

If the destination register is not one of WZR or XZR, LDAPR loads from memory with AcquirePC semantics.

For more information about memory ordering semantics, see Load-Acquire, Load-AcquirePC, and Store-Release.

For information about addressing modes, see Load/Store addressing modes.

It has encodings from 2 classes: Post-index and No offset

Post-index
(FEAT_LRCPC3)

313029282726252423222120191817161514131211109876543210
1x01100111000000000010RnRt
sizeL

Encoding for the 32-bit variant

Applies when (size == 10)

LDAPR <Wt>, [<Xn|SP>], #4

Encoding for the 64-bit variant

Applies when (size == 11)

LDAPR <Xt>, [<Xn|SP>], #8

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_LRCPC3) then EndOfDecode(Decode_UNDEF); end; let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); var wback : boolean = TRUE; let acquirepc : boolean = TRUE; let regsize : integer{} = if size == '11' then 64 else 32; let datasize : integer{} = 8 << UInt(size); let offset : integer = 1 << UInt(size); let tagchecked : boolean = TRUE; var wb_unknown : boolean = FALSE; if n == t && n != 31 then let c : Constraint = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD); assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_WBSUPPRESS => wback = FALSE; // writeback is suppressed when Constraint_UNKNOWN => wb_unknown = TRUE; // writeback is UNKNOWN when Constraint_UNDEF => EndOfDecode(Decode_UNDEF); when Constraint_NOP => EndOfDecode(Decode_NOP); end; end;

No offset
(FEAT_LRCPC)

313029282726252423222120191817161514131211109876543210
1x111000101(1)(1)(1)(1)(1)110000RnRt
sizeVRARRso3opc

Encoding for the 32-bit variant

Applies when (size == 10)

LDAPR <Wt>, [<Xn|SP> {, #0}]

Encoding for the 64-bit variant

Applies when (size == 11)

LDAPR <Xt>, [<Xn|SP> {, #0}]

Decode for all variants of this encoding

if !IsFeatureImplemented(FEAT_LRCPC) then EndOfDecode(Decode_UNDEF); end; let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let wback : boolean = FALSE; let offset : integer = 0; let wb_unknown : boolean = FALSE; let elsize : integer{} = 8 << UInt(size); let regsize : integer{} = if elsize == 64 then 64 else 32; let datasize : integer{} = elsize; let acquirepc : boolean = TRUE; let tagchecked : boolean = n != 31;

Assembler Symbols

<Wt>

Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Xt>

Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

Operation

var address : bits(64); var data : bits(datasize); let dbytes : integer{} = datasize DIV 8; let accdesc : AccessDescriptor = CreateAccDescLDAcqPC(tagchecked, acquirepc, t); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; data = Mem{datasize}(address, accdesc); X{regsize}(t) = ZeroExtend{regsize}(data); if wback then if wb_unknown then address = ARBITRARY : bits(64); else address = AddressAdd(address, offset, accdesc); end; if n == 31 then SP{64}() = address; else X{64}(n) = address; end; end;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2026-03_rel 2026-03-26 20:48:11

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