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LDPSW -- A64

LDPSW

Load pair of registers signed word

This instruction calculates an address from a base register value and an immediate offset, loads two 32-bit words from memory, sign-extends them, and writes them to two registers. For information about addressing modes, see Load/Store addressing modes.

It has encodings from 3 classes: Post-index , Pre-index and Signed offset

Post-index

313029282726252423222120191817161514131211109876543210
0110100011imm7Rt2RnRt
opcVRL

Encoding

LDPSW <Xt1>, <Xt2>, [<Xn|SP>], #<imm>

Decode for this encoding

var wback : boolean = TRUE; let postindex : boolean = TRUE;

Pre-index

313029282726252423222120191817161514131211109876543210
0110100111imm7Rt2RnRt
opcVRL

Encoding

LDPSW <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!

Decode for this encoding

var wback : boolean = TRUE; let postindex : boolean = FALSE;

Signed offset

313029282726252423222120191817161514131211109876543210
0110100101imm7Rt2RnRt
opcVRL

Encoding

LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]

Decode for this encoding

var wback : boolean = FALSE; let postindex : boolean = FALSE;

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDPSW.

Assembler Symbols

<Xt1>

Is the 64-bit name of the first general-purpose register to be transferred, encoded in the "Rt" field.

<Xt2>

Is the 64-bit name of the second general-purpose register to be transferred, encoded in the "Rt2" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<imm>

For the "Post-index" and "Pre-index" variants: is the signed immediate byte offset, a multiple of 4 in the range -256 to 252, encoded in the "imm7" field as <imm>/4.

For the "Signed offset" variant: is the optional signed immediate byte offset, a multiple of 4 in the range -256 to 252, defaulting to 0 and encoded in the "imm7" field as <imm>/4.

Shared Decode

let t : integer{} = UInt(Rt); let t2 : integer{} = UInt(Rt2); let n : integer{} = UInt(Rn); let nontemporal : boolean = FALSE; let scale : integer{} = 2 + UInt(opc[1]); let datasize : integer{} = 32; let offset : bits(64) = LSL(SignExtend{64}(imm7), scale); let tagchecked : boolean = wback || n != 31; var rt_unknown : boolean = FALSE; var wb_unknown : boolean = FALSE; if wback && (t == n || t2 == n) && n != 31 then let c : Constraint = ConstrainUnpredictable(Unpredictable_WBOVERLAPLD); assert c IN {Constraint_WBSUPPRESS, Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_WBSUPPRESS => wback = FALSE; // Writeback is suppressed when Constraint_UNKNOWN => wb_unknown = TRUE; // Writeback is UNKNOWN when Constraint_UNDEF => EndOfDecode(Decode_UNDEF); when Constraint_NOP => EndOfDecode(Decode_NOP); end; end; if t == t2 then let c : Constraint = ConstrainUnpredictable(Unpredictable_LDPOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN => rt_unknown = TRUE; // Result is UNKNOWN when Constraint_UNDEF => EndOfDecode(Decode_UNDEF); when Constraint_NOP => EndOfDecode(Decode_NOP); end; end;

Operation

var address : bits(64); var data1 : bits(datasize); var data2 : bits(datasize); let dbytes : integer{} = datasize DIV 8; let privileged : boolean = PSTATE.EL != EL0; let ispair : boolean = TRUE; let accdesc : AccessDescriptor = CreateAccDescGPR(MemOp_LOAD, nontemporal, privileged, tagchecked, ispair, t, t2); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; if !postindex then address = AddressAdd(address, offset, accdesc); end; let data : bits(2*datasize) = Mem{2*datasize}(address, accdesc); if rt_unknown then data1 = ARBITRARY : bits(datasize); data2 = ARBITRARY : bits(datasize); elsif BigEndian(accdesc.acctype) then data2 = data[(datasize-1):0]; data1 = data[(2*datasize-1):datasize]; else data1 = data[(datasize-1):0]; data2 = data[(2*datasize-1):datasize]; end; X{64}(t) = SignExtend{64}(data1); X{64}(t2) = SignExtend{64}(data2); if wback then if wb_unknown then address = ARBITRARY : bits(64); elsif postindex then address = AddressAdd(address, offset, accdesc); end; if n == 31 then SP{64}() = address; else X{64}(n) = address; end; end;

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.


2026-03_rel 2026-03-26 20:48:11

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