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MSRR -- A64

MSRR

Move two adjacent general-purpose registers to System register

This instruction allows the PE to write an AArch64 128-bit System register from two adjacent 64-bit general-purpose registers.

System
(FEAT_SYSREG128)

313029282726252423222120191817161514131211109876543210
110101010101o0op1CRnCRmop2Rt
L

Encoding

MSRR (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>), <Xt>, <Xt+1>

Decode for this encoding

if !IsFeatureImplemented(FEAT_SYSREG128) then EndOfDecode(Decode_UNDEF); end; if Rt[0] == '1' then EndOfDecode(Decode_UNDEF); end; let t : integer = UInt(Rt); let t2 : integer = UInt(Rt+1); let sys_L : bits(1) = L; let sys_op0 : bits(2) = '1' :: o0; let sys_op1 : bits(3) = op1; let sys_op2 : bits(3) = op2; let sys_crn : bits(4) = CRn; let sys_crm : bits(4) = CRm;

Assembler Symbols

<systemreg>

Is a System register name, encoded in "o0:op1:CRn:CRm:op2".

<op0>

Is an unsigned immediate, encoded in o0:

o0 <op0>
0 2
1 3
<op1>

Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field.

<Cn>

Is a name 'Cn', with 'n' in the range 0 to 15, encoded in the "CRn" field.

<Cm>

Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field.

<op2>

Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.

<Xt>

Is the 64-bit name of the first general-purpose source register, encoded in the "Rt" field.

<Xt+1>

Is the 64-bit name of the second general-purpose source register, encoded as "Rt" +1.


2026-03_rel 2026-03-26 20:48:11

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