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STLXRH -- A64
Base Instructions
SIMD&FP Instructions
SVE Instructions
SME Instructions
Index by Encoding
Shared Pseudocode
Proprietary Notice

STLXRH

Store-release exclusive register halfword

This instruction stores a halfword from a 32-bit register to memory if the PE has exclusive access to the memory address, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. See Synchronization and semaphores. The memory access is atomic. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.

313029282726252423222120191817161514131211109876543210
01001000000Rs1(1)(1)(1)(1)(1)RnRt
sizeLo0Rt2

Encoding

STLXRH <Ws>, <Wt>, [<Xn|SP>{, #0}]

Decode for this encoding

let s : integer{} = UInt(Rs); let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn); let acqrel : boolean = TRUE; let tagchecked : boolean = n != 31; var rt_unknown : boolean = FALSE; var rn_unknown : boolean = FALSE; if s == t then let c : Constraint = ConstrainUnpredictable(Unpredictable_DATAOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN => rt_unknown = TRUE; // store UNKNOWN value when Constraint_UNDEF => EndOfDecode(Decode_UNDEF); when Constraint_NOP => EndOfDecode(Decode_NOP); end; end; if s == n && n != 31 then let c : Constraint = ConstrainUnpredictable(Unpredictable_BASEOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN => rn_unknown = TRUE; // address is UNKNOWN when Constraint_UNDEF => EndOfDecode(Decode_UNDEF); when Constraint_NOP => EndOfDecode(Decode_NOP); end; end;

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly STLXRH.

Assembler Symbols

<Ws>

Is the 32-bit name of the general-purpose register into which the status result of the store exclusive is written, encoded in the "Rs" field. The value returned is:

0
If the operation updates memory.
1
If the operation fails to update memory.
<Wt>

Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Aborts and alignment

If a synchronous Data Abort exception is generated by the execution of this instruction:

A non halfword-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to the following rules:

If AArch64_ExclusiveMonitorsPass() returns FALSE and the memory address, if accessed, would generate a synchronous Data Abort exception, it is IMPLEMENTATION DEFINED whether the exception is generated.

Operation

var address : bits(64); var data : bits(16); let privileged : boolean = PSTATE.EL != EL0; let accdesc : AccessDescriptor = CreateAccDescExLDST(MemOp_STORE, acqrel, tagchecked, privileged, t); if n == 31 then CheckSPAlignment(); address = SP{64}(); elsif rn_unknown then address = ARBITRARY : bits(64); else address = X{64}(n); end; if rt_unknown then data = ARBITRARY : bits(16); else data = X{16}(t); end; var status : bit = '1'; // Check whether the Exclusives monitors are set to include the // physical memory locations corresponding to virtual address // range [address, address+dbytes-1]. // If AArch64_ExclusiveMonitorsPass() returns FALSE and the memory address, // if accessed, would generate a synchronous Data Abort exception, it is // IMPLEMENTATION DEFINED whether the exception is generated. // It is a limitation of this model that synchronous Data Aborts are never // generated in this case, as Mem is not called. // If FEAT_SPE is implemented, it is also IMPLEMENTATION DEFINED whether or not the // physical address packet is output when permitted and when // AArch64_ExclusiveMonitorPass() returns FALSE for a Store Exclusive instruction. // This behavior is not reflected here due to the previously stated limitation. if AArch64_ExclusiveMonitorsPass(address, 2, accdesc) then // This atomic write will be rejected if it does not refer // to the same physical locations after address translation. Mem{16}(address, accdesc) = data; status = ExclusiveMonitorsStatus(); end; X{32}(s) = ZeroExtend{32}(status);

Operational information

This instruction is a data-independent-time instruction as described in About PSTATE.DIT.

Base Instructions
SIMD&FP Instructions
SVE Instructions
SME Instructions
Index by Encoding
Shared Pseudocode
Proprietary Notice

2026-03_rel 2026-03-26 20:48:11

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