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STZGM -- A64

STZGM

Store Allocation Tag and zero multiple

This instruction writes a naturally aligned block of N Allocation Tags and stores zero to the associated data locations, where the size of N is identified in DCZID_EL0.BS, and the Allocation Tag is taken from the source register bits<3:0>.

This instruction is UNDEFINED at EL0. This instruction generates an Unchecked access.

Integer
(FEAT_MTE2)

313029282726252423222120191817161514131211109876543210
1101100100100000000000RnRt
opcimm9op2

Encoding

STZGM <Xt>, [<Xn|SP>]

Decode for this encoding

if !IsFeatureImplemented(FEAT_MTE2) then EndOfDecode(Decode_UNDEF); end; let t : integer{} = UInt(Rt); let n : integer{} = UInt(Rn);

Assembler Symbols

<Xt>

Is the 64-bit name of the general-purpose source register, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Operation

if PSTATE.EL == EL0 then Undefined(); end; let data : bits(64) = X{}(t); let tag : bits(4) = data[3:0]; var address : bits(64); if n == 31 then CheckSPAlignment(); address = SP{64}(); else address = X{64}(n); end; let size : integer{} = 4 * (2 ^ (UInt(DCZID_EL0().BS))); address = AlignDownSize(address, size); let count : integer = size >> LOG2_TAG_GRANULE; let stzgm : boolean = TRUE; let accdesc : AccessDescriptor = CreateAccDescLDGSTG(MemOp_STORE, stzgm, t); for i = 0 to count-1 do AArch64_MemTag(address, accdesc) = tag; Mem{8*TAG_GRANULE}(address, accdesc) = Zeros{8*TAG_GRANULE}; address = AddressIncrement(address, TAG_GRANULE, accdesc); end;


2026-03_rel 2026-03-26 20:48:11

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