Data-processing and miscellaneous instructions

!= 1111 00x != 1111 0 0

Multiply and Accumulate

0 0xxxx 1 00 1

Miscellaneous

0 10xx0 0 != 1111 0 0 0 1 0 0 0

UNALLOCATED

00 010

UNALLOCATED

00 011

Branch and Exchange (register)

01 001

Branch and Exchange to Jazelle (register)

01 010

Branch with Link and Exchange (register)

01 011

Count Leading Zeros

11 001

Exception Return

11 110

UNALLOCATED

1x 01x

UNALLOCATED

x0 001

Move special register (register)

000

Cyclic Redundancy Check

100

Integer Saturating Arithmetic

101

Exception Generation

111

UNALLOCATED

!= 11 110

Halfword Multiply and Accumulate

0 10xx0 1 0

Synchronization primitives and Load-Acquire/Store-Release

0 1xxxx 1 00 1 != 1111 0 0 0 1 1 0 0 1

UNALLOCATED

0

Load/Store Exclusive and Load-Acquire/Store-Release

1

Extra load/store

0 1 != 00 1 != 1111 0 0 0 1 != 00 1

Load/Store Dual, Half, Signed Byte (register)

0

Load/Store Dual, Half, Signed Byte (immediate, literal)

1

Data-processing register (register shift)

0 != 10xx0 0 1 != 1111 0 0 0 0 1

Integer Data Processing (three register, register shift)

0x

Integer Test and Compare (two register, register shift)

10 1

Logical Arithmetic (three register, register shift)

11

Data-processing register (immediate shift)

0 != 10xx0 0 != 1111 0 0 0 0

Integer Data Processing (three register, immediate shift)

0x

Integer Test and Compare (two register, immediate shift)

10 1

Logical Arithmetic (three register, immediate shift)

11

Data-processing immediate

1 != 1111 0 0 1

Integer Data Processing (two register and immediate)

0x

Move Halfword (immediate)

10 00

Move Special Register and Hints (immediate)

10 10

Integer Test and Compare (one register and immediate)

10 x1

Logical Arithmetic (two register and immediate)

11

Load/Store Word, Unsigned Byte (immediate, literal)

!= 1111 010

Load/Store Word, Unsigned Byte (register)

!= 1111 011 0

Media instructions

!= 1111 011 1 != 1111 0 1 1 1

Parallel Arithmetic

00xxx

UNALLOCATED

01000 001

Select Bytes

01000 101

Pack Halfword

01000 xx0

UNALLOCATED

01001 x01

UNALLOCATED

01001 xx0

UNALLOCATED

0110x 001

UNALLOCATED

0110x xx0

Saturate 16-bit

01x10 001

UNALLOCATED

01x10 101

Reverse Bit/Byte

01x11 x01

Saturate 32-bit

01x1x xx0

Extend and Add

01xxx 011

UNALLOCATED

01xxx 111

Signed multiply, Divide

10xxx

Unsigned Sum of Absolute Differences

11000 000

UNALLOCATED

11001 000

UNALLOCATED

1100x 10x

UNALLOCATED

1101x 111

Bitfield Insert

1110x x00

UNALLOCATED

11110 111

Permanently UNDEFINED

11111 111

UNALLOCATED

11x0x 001

UNALLOCATED

11x0x x1x

UNALLOCATED

11x1x 011

UNALLOCATED

11x1x x0x

Bitfield Extract

11x1x x10

UNALLOCATED

x110x 101

Branch, branch with link, and block data transfer

10x 1 0

Exception Save/Restore

1111 0

Branch (immediate)

1

Load/Store Multiple

!= 1111 0

System register access, Advanced SIMD, floating-point, and Supervisor call

11x 1 1

Unconditional Advanced SIMD and floating-point instructions

1111 != 11 1x 1 1 1 1 1 1 != 11x 1

Advanced SIMD three registers of the same length extension

0xx 0x

UNALLOCATED

0xx 1x

Floating-point conditional select

100 0 != 00 0 0

UNALLOCATED

100 0 != 00 1 0

Floating-point minNum/maxNum

101 00xxxx 0 != 00 0

UNALLOCATED

101 01xxxx 0 != 00 0

UNALLOCATED

101 10xxxx 0 != 00 0

Floating-point extraction and insertion

101 110000 0 != 00 1 0

UNALLOCATED

101 110001 0 != 00 1 0

UNALLOCATED

101 11001x 0 != 00 1 0

UNALLOCATED

101 1101xx 0 != 00 1 0

Floating-point directed convert to integer

101 111xxx 0 != 00 1 0

UNALLOCATED

101 11xxxx 0 != 00 0 0

Advanced SIMD and floating-point multiply with accumulate

10x 0 00

UNALLOCATED

10x 0 != 00 1

Advanced SIMD and floating-point dot product

10x 1 0x

UNALLOCATED

10x 1 1x

Supervisor call

11 1 1 1 1

UNALLOCATED

1111

Supervisor Call

!= 1111

UNALLOCATED

!= 11 0x

Advanced SIMD and System register load/store and 64-bit move

!= 1111 0x 1x != 1111 1 1 0 1

Advanced SIMD and floating-point 64-bit move

00x0 0x

System register 64-bit move

00x0 11

UNALLOCATED

10

Advanced SIMD and floating-point load/store

!= 00x0 0x

System register load/store

!= 00x0 11

Floating-point data-processing

!= 1111 10 10 0 != 1111 1 1 1 0 1 0 0

Floating-point move immediate

1x11 0

Floating-point data-processing (two registers)

1x11 1

Floating-point data-processing (three registers)

!= 1x11

UNALLOCATED

!= 1111 10 11 0

Advanced SIMD and System register 32-bit move

!= 1111 10 1x 1 != 1111 1 1 1 0 1 1

UNALLOCATED

000 000

Floating-point 16-bit move

000 001

Floating-point 32-bit move

000 010

UNALLOCATED

000 10x

UNALLOCATED

0x1 010

UNALLOCATED

10x 010

Floating-point move special register

111 010

UNALLOCATED

x10 010

Advanced SIMD 8/16/32-bit element move/duplicate

011

System register 32-bit move

11x

UNALLOCATED

!= 000 x0x

Unconditional instructions

1111 0xx 1 1 1 1 0

Miscellaneous

00x 1 1 1 1 0 0 0

UNALLOCATED

0xxxx

Change Process State

10000 xx0x

SETPAN

10001 0000

UNALLOCATED

10001 0001

UNALLOCATED

10001 010x

UNALLOCATED

10001 1x0x

UNALLOCATED

1000x xx1x

UNALLOCATED

10010 0011

UNALLOCATED

10010 0110

UNPREDICTABLE

10010 0111

UNALLOCATED

10010 1x1x

UNALLOCATED

10011 0011

UNALLOCATED

10011 011x

UNALLOCATED

10011 1x1x

UNALLOCATED

1001x 0010

UNALLOCATED

1001x xx0x

UNALLOCATED

101xx

UNALLOCATED

11xxx

Advanced SIMD data-processing

01x 1 1 1 1 0 0 1

Advanced SIMD three registers of the same length

0

Advanced SIMD two registers, or three registers of different lengths

1 0 1 1 1 1 0 0 1 1 0

Advanced SIMD vector extract

0 11

Advanced SIMD two registers misc

1 11 0x

Advanced SIMD table permute

1 11 10

Advanced SIMD duplicate (scalar)

1 11 11

Advanced SIMD three registers of different lengths

!= 11 0

Advanced SIMD two registers and a scalar

!= 11 1

Advanced SIMD shifts and immediate generation

1 1 1 1 1 1 0 0 1 1 1

Advanced SIMD one register and modified immediate

000xxxxxxxxxxx0

Advanced SIMD two registers and shift amount

!= 000xxxxxxxxxxx0

Advanced SIMD element or structure load/store

100 0 1 1 1 1 0 1 0 0 0

Advanced SIMD load/store multiple structures

0

Advanced SIMD load single structure to all lanes

1 11

Advanced SIMD load/store single structure to one lane

1 != 11

UNALLOCATED

101 0

UNALLOCATED

11x 0

Memory hints and barriers

1xx 1 1 1 1 1 0 1 1

UNPREDICTABLE

00xx1

UNPREDICTABLE

01001

Barriers

01011

UNPREDICTABLE

011x1

Preload (immediate)

0xxx0

Preload (register)

1xxx0 0

UNPREDICTABLE

1xxx1 0

UNALLOCATED

1xxxx 1 Instruction bits Encoding Group 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 Branch, branch with link, and block data transfer 1 1 System register access, Advanced SIMD, floating-point, and Supervisor call 1111 0 Unconditional instructions != 1111 0 0 Data-processing and miscellaneous instructions != 1111 010 Load/Store Word, Unsigned Byte (immediate, literal) != 1111 011 0 Load/Store Word, Unsigned Byte (register) != 1111 0 1 1 1 Media instructions Instruction bits Instruction class 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 != 1111 0 0 0 1 != 00 1 Extra load/store != 1111 0 0 0 0 1 00 1 Multiply and Accumulate != 1111 0 0 0 1 1 00 1 Synchronization primitives and Load-Acquire/Store-Release != 1111 0 0 0 1 0 0 0 Miscellaneous != 1111 0 0 0 1 0 0 1 0 Halfword Multiply and Accumulate != 1111 0 0 0 n z z 0 Data-processing register (immediate shift) != 1111 0 0 0 n z z 0 1 Data-processing register (register shift) != 1111 0 0 1 Data-processing immediate != 1111 0 1 1 0 0 1 Parallel Arithmetic != 1111 0 1 1 0 1 011 1 Extend and Add != 1111 0 1 1 0 1 1 0 1 Saturate 32-bit != 1111 0 1 1 0 1 1 0 001 1 Saturate 16-bit != 1111 0 1 1 0 1 1 1 0 1 1 Reverse Bit/Byte != 1111 0 1 1 01000 0 1 Pack Halfword != 1111 0 1 1 01000 101 1 Select Bytes != 1111 0 1 1 1 0 1 Signed multiply, Divide != 1111 0 1 1 1 1 1 1 0 1 Bitfield Extract != 1111 0 1 1 11000 000 1 Unsigned Sum of Absolute Differences != 1111 0 1 1 1 1 1 0 0 0 1 Bitfield Insert != 1111 0 1 1 11111 111 1 Permanently UNDEFINED 1 0 1 Branch (immediate) 1111 1 0 0 Exception Save/Restore != 1111 1 0 0 Load/Store Multiple 1 1 11 Supervisor call 1111 1 1 != 11x 1 Unconditional Advanced SIMD and floating-point instructions != 1111 1 1 0 1 Advanced SIMD and System register load/store and 64-bit move != 1111 1 1 1 0 1 1 Advanced SIMD and System register 32-bit move != 1111 1 1 1 0 1 0 0 Floating-point data-processing 1111 0 0 0 Miscellaneous 1111 0 0 1 Advanced SIMD data-processing 1111 0 1 1 Memory hints and barriers 1111 0 1 0 0 0 Advanced SIMD element or structure load/store Data-processing and miscellaneous instructions != 1111 0 0 1 0 Decode fields Instruction page Encoding opc S Rn 000 0 AND, ANDS (immediate) AND 000 1 AND, ANDS (immediate) ANDS 001 0 EOR, EORS (immediate) EOR 001 1 EOR, EORS (immediate) EORS 010 0 1101 SUB, SUBS (SP minus immediate) SUB 010 0 1111 ADR A2 010 0 != 11x1 SUB, SUBS (immediate) SUB 010 1 1101 SUB, SUBS (SP minus immediate) SUBS 010 1 != 1101 SUB, SUBS (immediate) SUBS 011 0 RSB, RSBS (immediate) RSB 011 1 RSB, RSBS (immediate) RSBS 100 0 1101 ADD, ADDS (SP plus immediate) ADD 100 0 1111 ADR A1 100 0 != 11x1 ADD, ADDS (immediate) ADD 100 1 1101 ADD, ADDS (SP plus immediate) ADDS 100 1 != 1101 ADD, ADDS (immediate) ADDS 101 0 ADC, ADCS (immediate) ADC 101 1 ADC, ADCS (immediate) ADCS 110 0 SBC, SBCS (immediate) SBC 110 1 SBC, SBCS (immediate) SBCS 111 0 RSC, RSCS (immediate) RSC 111 1 RSC, RSCS (immediate) RSCS != 1111 0 0 1 1 0 0 0 Decode fields Instruction page Encoding H 0 MOV, MOVS (immediate) A2 1 MOVT A1 != 1111 0 0 1 1 0 1 0 (1) (1) (1) (1) Decode fields Instruction page Encoding R:imm4 imm12 00000 xxxxx101xxxx Reserved hint, behaves as NOP 00000 xxxx0x1xxxxx Reserved hint, behaves as NOP 00000 xxxx000x1xxx Reserved hint, behaves as NOP 00000 xxxx00000000 NOP A1 00000 xxxx00000001 YIELD A1 00000 xxxx00000010 WFE A1 00000 xxxx00000011 WFI A1 00000 xxxx00000100 SEV A1 00000 xxxx00000101 SEVL A1 00000 xxxx0000011x Reserved hint, behaves as NOP 00000 xxxx00010xx1 Reserved hint, behaves as NOP 00000 xxxx00010000 ESB A1 00000 xxxx00010010 TSB A1 00000 xxxx00010100 CSDB A1 00000 xxxx00010110 CLRBHB A1 00000 xxxx0100xxxx Reserved hint, behaves as NOP 00000 xxxx10xxxxxx Reserved hint, behaves as NOP 00000 xxxx11x0xxxx Reserved hint, behaves as NOP 00000 xxxx1111xxxx DBG A1 != 00000 MSR (immediate) != 1111 0 0 1 1 0 1 (0) (0) (0) (0) Decode fields Instruction page Encoding opc 00 TST (immediate) A1 01 TEQ (immediate) A1 10 CMP (immediate) A1 11 CMN (immediate) A1 != 1111 0 0 1 1 1 Decode fields Instruction page Encoding opc S 00 0 ORR, ORRS (immediate) ORR 00 1 ORR, ORRS (immediate) ORRS 01 0 MOV, MOVS (immediate) MOV 01 1 MOV, MOVS (immediate) MOVS 10 0 BIC, BICS (immediate) BIC 10 1 BIC, BICS (immediate) BICS 11 0 MVN, MVNS (immediate) MVN 11 1 MVN, MVNS (immediate) MVNS != 1111 0 0 0 0 0 Decode fields Instruction page Encoding opc S Rn imm5:stype 000 0 0000011 AND, ANDS (register) AND, rotate right with extend 000 0 != 0000011 AND, ANDS (register) AND, shift or rotate by value 000 1 0000011 AND, ANDS (register) ANDS, rotate right with extend 000 1 != 0000011 AND, ANDS (register) ANDS, shift or rotate by value 001 0 0000011 EOR, EORS (register) EOR, rotate right with extend 001 0 != 0000011 EOR, EORS (register) EOR, shift or rotate by value 001 1 0000011 EOR, EORS (register) EORS, rotate right with extend 001 1 != 0000011 EOR, EORS (register) EORS, shift or rotate by value 010 0 1101 0000011 SUB, SUBS (SP minus register) SUB, rotate right with extend 010 0 1101 != 0000011 SUB, SUBS (SP minus register) SUB, shift or rotate by value 010 0 != 1101 0000011 SUB, SUBS (register) SUB, rotate right with extend 010 0 != 1101 != 0000011 SUB, SUBS (register) SUB, shift or rotate by value 010 1 1101 0000011 SUB, SUBS (SP minus register) SUBS, rotate right with extend 010 1 1101 != 0000011 SUB, SUBS (SP minus register) SUBS, shift or rotate by value 010 1 != 1101 0000011 SUB, SUBS (register) SUBS, rotate right with extend 010 1 != 1101 != 0000011 SUB, SUBS (register) SUBS, shift or rotate by value 011 0 0000011 RSB, RSBS (register) RSB, rotate right with extend 011 0 != 0000011 RSB, RSBS (register) RSB, shift or rotate by value 011 1 0000011 RSB, RSBS (register) RSBS, rotate right with extend 011 1 != 0000011 RSB, RSBS (register) RSBS, shift or rotate by value 100 0 1101 0000011 ADD, ADDS (SP plus register) ADD, rotate right with extend 100 0 1101 != 0000011 ADD, ADDS (SP plus register) ADD, shift or rotate by value 100 0 != 1101 0000011 ADD, ADDS (register) ADD, rotate right with extend 100 0 != 1101 != 0000011 ADD, ADDS (register) ADD, shift or rotate by value 100 1 1101 0000011 ADD, ADDS (SP plus register) ADDS, rotate right with extend 100 1 1101 != 0000011 ADD, ADDS (SP plus register) ADDS, shift or rotate by value 100 1 != 1101 0000011 ADD, ADDS (register) ADDS, rotate right with extend 100 1 != 1101 != 0000011 ADD, ADDS (register) ADDS, shift or rotate by value 101 0 0000011 ADC, ADCS (register) ADC, rotate right with extend 101 0 != 0000011 ADC, ADCS (register) ADC, shift or rotate by value 101 1 0000011 ADC, ADCS (register) ADCS, rotate right with extend 101 1 != 0000011 ADC, ADCS (register) ADCS, shift or rotate by value 110 0 0000011 SBC, SBCS (register) SBC, rotate right with extend 110 0 != 0000011 SBC, SBCS (register) SBC, shift or rotate by value 110 1 0000011 SBC, SBCS (register) SBCS, rotate right with extend 110 1 != 0000011 SBC, SBCS (register) SBCS, shift or rotate by value 111 0 0000011 RSC, RSCS (register) RSC, rotate right with extend 111 0 != 0000011 RSC, RSCS (register) RSC, shift or rotate by value 111 1 0000011 RSC, RSCS (register) RSCS, rotate right with extend 111 1 != 0000011 RSC, RSCS (register) RSCS, shift or rotate by value != 1111 0 0 0 1 0 1 (0) (0) (0) (0) 0 Decode fields Instruction page Encoding opc imm5:stype 00 0000011 TST (register) Rotate right with extend 00 != 0000011 TST (register) Shift or rotate by value 01 0000011 TEQ (register) Rotate right with extend 01 != 0000011 TEQ (register) Shift or rotate by value 10 0000011 CMP (register) Rotate right with extend 10 != 0000011 CMP (register) Shift or rotate by value 11 0000011 CMN (register) Rotate right with extend 11 != 0000011 CMN (register) Shift or rotate by value != 1111 0 0 0 1 1 0 Decode fields Instruction page Encoding opc S imm5:stype 00 0 0000011 ORR, ORRS (register) ORR, rotate right with extend 00 0 != 0000011 ORR, ORRS (register) ORR, shift or rotate by value 00 1 0000011 ORR, ORRS (register) ORRS, rotate right with extend 00 1 != 0000011 ORR, ORRS (register) ORRS, shift or rotate by value 01 0 0000011 MOV, MOVS (register) MOV, rotate right with extend 01 0 != 0000011 MOV, MOVS (register) MOV, shift or rotate by value 01 1 0000011 MOV, MOVS (register) MOVS, rotate right with extend 01 1 != 0000011 MOV, MOVS (register) MOVS, shift or rotate by value 10 0 0000011 BIC, BICS (register) BIC, rotate right with extend 10 0 != 0000011 BIC, BICS (register) BIC, shift or rotate by value 10 1 0000011 BIC, BICS (register) BICS, rotate right with extend 10 1 != 0000011 BIC, BICS (register) BICS, shift or rotate by value 11 0 0000011 MVN, MVNS (register) MVN, rotate right with extend 11 0 != 0000011 MVN, MVNS (register) MVN, shift or rotate by value 11 1 0000011 MVN, MVNS (register) MVNS, rotate right with extend 11 1 != 0000011 MVN, MVNS (register) MVNS, shift or rotate by value != 1111 0 0 0 0 0 1 Decode fields Instruction page Encoding opc S 000 0 AND, ANDS (register-shifted register) Not flag setting 000 1 AND, ANDS (register-shifted register) Flag setting 001 0 EOR, EORS (register-shifted register) Not flag setting 001 1 EOR, EORS (register-shifted register) Flag setting 010 0 SUB, SUBS (register-shifted register) Not flag setting 010 1 SUB, SUBS (register-shifted register) Flag setting 011 0 RSB, RSBS (register-shifted register) Not flag setting 011 1 RSB, RSBS (register-shifted register) Flag setting 100 0 ADD, ADDS (register-shifted register) Not flag setting 100 1 ADD, ADDS (register-shifted register) Flag setting 101 0 ADC, ADCS (register-shifted register) Not flag setting 101 1 ADC, ADCS (register-shifted register) Flag setting 110 0 SBC, SBCS (register-shifted register) Not flag setting 110 1 SBC, SBCS (register-shifted register) Flag setting 111 0 RSC, RSCS (register-shifted register) Not flag setting 111 1 RSC, RSCS (register-shifted register) Flag setting != 1111 0 0 0 1 0 1 (0) (0) (0) (0) 0 1 Decode fields Instruction page Encoding opc 00 TST (register-shifted register) 01 TEQ (register-shifted register) 10 CMP (register-shifted register) 11 CMN (register-shifted register) != 1111 0 0 0 1 1 0 1 Decode fields Instruction page Encoding opc S 00 0 ORR, ORRS (register-shifted register) Not flag setting 00 1 ORR, ORRS (register-shifted register) Flag setting 01 0 MOV, MOVS (register-shifted register) Not flag setting 01 1 MOV, MOVS (register-shifted register) Flag setting 10 0 BIC, BICS (register-shifted register) Not flag setting 10 1 BIC, BICS (register-shifted register) Flag setting 11 0 MVN, MVNS (register-shifted register) Not flag setting 11 1 MVN, MVNS (register-shifted register) Flag setting != 1111 0 0 0 0 (0) (0) (0) (0) 1 != 00 1 Decode fields Instruction page Encoding P W o1 op2 0 0 0 01 STRH (register) Post-indexed 0 0 0 10 LDRD (register) Post-indexed 0 0 0 11 STRD (register) Post-indexed 0 0 1 01 LDRH (register) Post-indexed 0 0 1 10 LDRSB (register) Post-indexed 0 0 1 11 LDRSH (register) Post-indexed 0 1 0 01 STRHT A2 0 1 0 1x UNALLOCATED 0 1 1 01 LDRHT A2 0 1 1 10 LDRSBT A2 0 1 1 11 LDRSHT A2 1 0 0 01 STRH (register) Offset 1 0 0 10 LDRD (register) Offset 1 0 0 11 STRD (register) Offset 1 0 1 01 LDRH (register) Offset 1 0 1 10 LDRSB (register) Offset 1 0 1 11 LDRSH (register) Offset 1 1 0 01 STRH (register) Pre-indexed 1 1 0 10 LDRD (register) Pre-indexed 1 1 0 11 STRD (register) Pre-indexed 1 1 1 01 LDRH (register) Pre-indexed 1 1 1 10 LDRSB (register) Pre-indexed 1 1 1 11 LDRSH (register) Pre-indexed != 1111 0 0 0 1 1 != 00 1 Decode fields Instruction page Encoding P:W o1 Rn op2 0 1111 10 LDRD (literal) A1 00 0 01 STRH (immediate) Post-indexed 01 0 01 STRHT A1 01 0 11 UNALLOCATED 00 0 11 STRD (immediate) Post-indexed 01 0 0xxx 10 UNALLOCATED 01 0 10xx 10 UNALLOCATED 01 0 110x 10 UNALLOCATED 01 0 1110 10 UNALLOCATED 00 0 != 1111 10 LDRD (immediate) Post-indexed 01 1 01 LDRHT A1 01 1 10 LDRSBT A1 01 1 11 LDRSHT A1 00 1 != 1111 01 LDRH (immediate) Post-indexed 00 1 != 1111 10 LDRSB (immediate) Post-indexed 00 1 != 1111 11 LDRSH (immediate) Post-indexed 10 0 01 STRH (immediate) Offset 11 0 01 STRH (immediate) Pre-indexed 10 0 11 STRD (immediate) Offset 11 0 11 STRD (immediate) Pre-indexed 10 0 != 1111 10 LDRD (immediate) Offset 11 0 != 1111 10 LDRD (immediate) Pre-indexed 10 1 != 1111 01 LDRH (immediate) Offset 11 1 != 1111 01 LDRH (immediate) Pre-indexed 10 1 != 1111 10 LDRSB (immediate) Offset 11 1 != 1111 10 LDRSB (immediate) Pre-indexed 10 1 != 1111 11 LDRSH (immediate) Offset 11 1 != 1111 11 LDRSH (immediate) Pre-indexed != 01 1 1111 01 LDRH (literal) A1 != 01 1 1111 10 LDRSB (literal) A1 != 01 1 1111 11 LDRSH (literal) A1 != 1111 0 0 0 1 0 0 1 0 Decode fields Instruction page Encoding opc M N 00 0 0 SMLABB, SMLABT, SMLATB, SMLATT SMLABB 00 0 1 SMLABB, SMLABT, SMLATB, SMLATT SMLATB 00 1 0 SMLABB, SMLABT, SMLATB, SMLATT SMLABT 00 1 1 SMLABB, SMLABT, SMLATB, SMLATT SMLATT 01 0 0 SMLAWB, SMLAWT SMLAWB 01 0 1 SMULWB, SMULWT SMULWB 01 1 0 SMLAWB, SMLAWT SMLAWT 01 1 1 SMULWB, SMULWT SMULWT 10 0 0 SMLALBB, SMLALBT, SMLALTB, SMLALTT SMLALBB 10 0 1 SMLALBB, SMLALBT, SMLALTB, SMLALTT SMLALTB 10 1 0 SMLALBB, SMLALBT, SMLALTB, SMLALTT SMLALBT 10 1 1 SMLALBB, SMLALBT, SMLALTB, SMLALTT SMLALTT 11 0 0 SMULBB, SMULBT, SMULTB, SMULTT SMULBB 11 0 1 SMULBB, SMULBT, SMULTB, SMULTT SMULTB 11 1 0 SMULBB, SMULBT, SMULTB, SMULTT SMULBT 11 1 1 SMULBB, SMULBT, SMULTB, SMULTT SMULTT != 1111 0 0 0 1 0 0 1 0 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 0 0 0 1 Instruction page Encoding BX A1 != 1111 0 0 0 1 0 0 1 0 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 0 0 1 0 Instruction page Encoding BXJ A1 != 1111 0 0 0 1 0 0 1 0 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 0 0 1 1 Instruction page Encoding BLX (register) A1 != 1111 0 0 0 1 0 1 1 0 (1) (1) (1) (1) (1) (1) (1) (1) 0 0 0 1 Instruction page Encoding CLZ A1 != 1111 0 0 0 1 0 1 1 0 (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) 0 1 1 0 (1) (1) (1) (0) Instruction page Encoding ERET A1 != 1111 0 0 0 1 0 0 0 1 1 1 Decode fields Instruction page Encoding opc 00 HLT A1 01 BKPT A1 10 HVC A1 11 SMC A1 != 1111 0 0 0 1 0 0 (0) (0) 0 0 0 0 Decode fields Instruction page Encoding opc B x0 0 MRS A1 x0 1 MRS (Banked register) A1 x1 0 MSR (register) A1 x1 1 MSR (Banked register) A1 != 1111 0 0 0 1 0 0 (0) (0) (0) 0 1 0 0 Decode fields Instruction page Encoding sz C 00 0 CRC32 CRC32B 00 1 CRC32C CRC32CB 01 0 CRC32 CRC32H 01 1 CRC32C CRC32CH 10 0 CRC32 CRC32W 10 1 CRC32C CRC32CW 11 UNPREDICTABLE != 1111 0 0 0 1 0 0 (0) (0) (0) (0) 0 1 0 1 Decode fields Instruction page Encoding opc 00 QADD A1 01 QSUB A1 10 QDADD A1 11 QDSUB A1 != 1111 0 0 0 0 1 0 0 1 Decode fields Instruction page Encoding opc S 000 0 MUL, MULS Not flag setting 000 1 MUL, MULS Flag setting 001 0 MLA, MLAS Not flag setting 001 1 MLA, MLAS Flag setting 01x 1 UNALLOCATED 010 0 UMAAL A1 011 0 MLS A1 100 0 UMULL, UMULLS Not flag setting 100 1 UMULL, UMULLS Flag setting 101 0 UMLAL, UMLALS Not flag setting 101 1 UMLAL, UMLALS Flag setting 110 0 SMULL, SMULLS Not flag setting 110 1 SMULL, SMULLS Flag setting 111 0 SMLAL, SMLALS Not flag setting 111 1 SMLAL, SMLALS Flag setting != 1111 0 0 0 1 1 (1) (1) 1 0 0 1 Decode fields Instruction page Encoding size L ex ord 0 1 UNALLOCATED 00 0 0 0 STL A1 00 0 1 0 STLEX A1 00 0 1 1 STREX A1 00 1 0 0 LDA A1 00 1 1 0 LDAEX A1 00 1 1 1 LDREX A1 01 0 0 UNALLOCATED 01 0 1 0 STLEXD A1 01 0 1 1 STREXD A1 01 1 1 0 LDAEXD A1 01 1 1 1 LDREXD A1 10 0 0 0 STLB A1 10 0 1 0 STLEXB A1 10 0 1 1 STREXB A1 10 1 0 0 LDAB A1 10 1 1 0 LDAEXB A1 10 1 1 1 LDREXB A1 11 0 0 0 STLH A1 11 0 1 0 STLEXH A1 11 0 1 1 STREXH A1 11 1 0 0 LDAH A1 11 1 1 0 LDAEXH A1 11 1 1 1 LDREXH A1 Load/Store Word, Unsigned Byte (immediate, literal) != 1111 0 1 0 Decode fields Instruction page Encoding P:W op2 op1 Rn 00 0 0 STR (immediate) Post-indexed 01 0 0 STRT A1 01 0 1 LDRT A1 00 0 1 != 1111 LDR (immediate) Post-indexed 00 1 0 STRB (immediate) Post-indexed 01 1 0 STRBT A1 01 1 1 LDRBT A1 00 1 1 != 1111 LDRB (immediate) Post-indexed 10 0 0 STR (immediate) Offset 11 0 0 STR (immediate) Pre-indexed 10 0 1 != 1111 LDR (immediate) Offset 11 0 1 != 1111 LDR (immediate) Pre-indexed 10 1 0 STRB (immediate) Offset 11 1 0 STRB (immediate) Pre-indexed 10 1 1 != 1111 LDRB (immediate) Offset 11 1 1 != 1111 LDRB (immediate) Pre-indexed != 01 0 1 1111 LDR (literal) A1 != 01 1 1 1111 LDRB (literal) A1 Load/Store Word, Unsigned Byte (register) != 1111 0 1 1 0 Decode fields Instruction page Encoding P op2 W op1 0 0 0 0 STR (register) Post-indexed 0 0 0 1 LDR (register) Post-indexed 0 0 1 0 STRT A2 0 0 1 1 LDRT A2 0 1 0 0 STRB (register) Post-indexed 0 1 0 1 LDRB (register) Post-indexed 0 1 1 0 STRBT A2 0 1 1 1 LDRBT A2 1 0 0 0 STR (register) Offset 1 0 0 1 LDR (register) Offset 1 0 1 0 STR (register) Pre-indexed 1 0 1 1 LDR (register) Pre-indexed 1 1 0 0 STRB (register) Offset 1 1 0 1 LDRB (register) Offset 1 1 1 0 STRB (register) Pre-indexed 1 1 1 1 LDRB (register) Pre-indexed Media instructions != 1111 0 1 1 1 1 1 1 0 1 Decode fields Instruction page Encoding U 0 SBFX A1 1 UBFX A1 != 1111 0 1 1 1 1 1 0 0 0 1 Decode fields Instruction page Encoding Rn 1111 BFC A1 != 1111 BFI A1 != 1111 0 1 1 0 1 (0) (0) 0 1 1 1 Decode fields Instruction page Encoding U op Rn 01 UNALLOCATED 0 00 1111 SXTB16 A1 0 00 != 1111 SXTAB16 A1 0 10 1111 SXTB A1 0 10 != 1111 SXTAB A1 0 11 1111 SXTH A1 0 11 != 1111 SXTAH A1 1 00 1111 UXTB16 A1 1 00 != 1111 UXTAB16 A1 1 10 1111 UXTB A1 1 10 != 1111 UXTAB A1 1 11 1111 UXTH A1 1 11 != 1111 UXTAH A1 != 1111 0 1 1 0 1 0 0 0 0 1 Decode fields Instruction page Encoding tb 0 PKHBT, PKHTB PKHBT 1 PKHBT, PKHTB PKHTB != 1111 0 1 1 0 0 (1) (1) (1) (1) 1 Decode fields Instruction page Encoding op1 B op2 xx1 1 01 UNALLOCATED xx1 1 10 UNALLOCATED x00 UNALLOCATED x10 1 01 UNALLOCATED x10 1 10 UNALLOCATED 001 0 00 SADD16 A1 001 0 01 SASX A1 001 0 10 SSAX A1 001 0 11 SSUB16 A1 001 1 00 SADD8 A1 001 1 11 SSUB8 A1 010 0 00 QADD16 A1 010 0 01 QASX A1 010 0 10 QSAX A1 010 0 11 QSUB16 A1 010 1 00 QADD8 A1 010 1 11 QSUB8 A1 011 0 00 SHADD16 A1 011 0 01 SHASX A1 011 0 10 SHSAX A1 011 0 11 SHSUB16 A1 011 1 00 SHADD8 A1 011 1 11 SHSUB8 A1 101 0 00 UADD16 A1 101 0 01 UASX A1 101 0 10 USAX A1 101 0 11 USUB16 A1 101 1 00 UADD8 A1 101 1 11 USUB8 A1 110 0 00 UQADD16 A1 110 0 01 UQASX A1 110 0 10 UQSAX A1 110 0 11 UQSUB16 A1 110 1 00 UQADD8 A1 110 1 11 UQSUB8 A1 111 0 00 UHADD16 A1 111 0 01 UHASX A1 111 0 10 UHSAX A1 111 0 11 UHSUB16 A1 111 1 00 UHADD8 A1 111 1 11 UHSUB8 A1 != 1111 0 1 1 1 1 1 1 1 1 1 1 1 Decode fields Instruction page Encoding cond 0xxx UNALLOCATED 10xx UNALLOCATED 110x UNALLOCATED 1110 UDF A1 != 1111 0 1 1 0 1 1 1 (1) (1) (1) (1) (1) (1) (1) (1) 0 1 1 Decode fields Instruction page Encoding o1 o2 0 0 REV A1 0 1 REV16 A1 1 0 RBIT A1 1 1 REVSH A1 != 1111 0 1 1 0 1 1 0 (1) (1) (1) (1) 0 0 1 1 Decode fields Instruction page Encoding U 0 SSAT16 A1 1 USAT16 A1 != 1111 0 1 1 0 1 1 0 1 Decode fields Instruction page Encoding U sh 0 0 SSAT Logical shift left 0 1 SSAT Arithmetic shift right 1 0 USAT Logical shift left 1 1 USAT Arithmetic shift right != 1111 0 1 1 0 1 0 0 0 (1) (1) (1) (1) 1 0 1 1 Instruction page Encoding SEL A1 != 1111 0 1 1 1 0 1 Decode fields Instruction page Encoding op1 Ra op2 0xx 1xx UNALLOCATED 0x1 0x1 UNALLOCATED 0x1 010 UNALLOCATED 000 1111 000 SMUAD, SMUADX SMUAD 000 1111 001 SMUAD, SMUADX SMUADX 000 1111 010 SMUSD, SMUSDX SMUSD 000 1111 011 SMUSD, SMUSDX SMUSDX 000 != 1111 000 SMLAD, SMLADX SMLAD 000 != 1111 001 SMLAD, SMLADX SMLADX 000 != 1111 010 SMLSD, SMLSDX SMLSD 000 != 1111 011 SMLSD, SMLSDX SMLSDX 001 000 SDIV A1 010 0xx UNALLOCATED 011 000 UDIV A1 100 000 SMLALD, SMLALDX SMLALD 100 001 SMLALD, SMLALDX SMLALDX 100 010 SMLSLD, SMLSLDX SMLSLD 100 011 SMLSLD, SMLSLDX SMLSLDX 100 1xx UNALLOCATED 101 01x UNALLOCATED 101 10x UNALLOCATED 101 110 SMMLS, SMMLSR SMMLS 101 111 SMMLS, SMMLSR SMMLSR 101 1111 000 SMMUL, SMMULR SMMUL 101 1111 001 SMMUL, SMMULR SMMULR 101 != 1111 000 SMMLA, SMMLAR SMMLA 101 != 1111 001 SMMLA, SMMLAR SMMLAR 11x UNALLOCATED != 1111 0 1 1 1 1 0 0 0 0 0 0 1 Decode fields Instruction page Encoding Ra 1111 USAD8 A1 != 1111 USADA8 A1 Branch, branch with link, and block data transfer 1 0 1 Decode fields Instruction page Encoding cond H 1111 BL, BLX (immediate) A2 != 1111 0 B A1 != 1111 1 BL, BLX (immediate) A1 1 1 1 1 1 0 0 Decode fields Instruction page Encoding P U S L 0 0 UNALLOCATED 1 1 UNALLOCATED 0 0 0 1 RFE, RFEDA, RFEDB, RFEIA, RFEIB Decrement After 0 0 1 0 SRS, SRSDA, SRSDB, SRSIA, SRSIB Decrement After 0 1 0 1 RFE, RFEDA, RFEDB, RFEIA, RFEIB Increment After 0 1 1 0 SRS, SRSDA, SRSDB, SRSIA, SRSIB Increment After 1 0 0 1 RFE, RFEDA, RFEDB, RFEIA, RFEIB Decrement Before 1 0 1 0 SRS, SRSDA, SRSDB, SRSIA, SRSIB Decrement Before 1 1 0 1 RFE, RFEDA, RFEDB, RFEIA, RFEIB Increment Before 1 1 1 0 SRS, SRSDA, SRSDB, SRSIA, SRSIB Increment Before != 1111 1 0 0 Decode fields Instruction page Encoding P U op L register_list 1 0 STM (User registers) 1 1 0xxxxxxxxxxxxxxx LDM (User registers) 1 1 1xxxxxxxxxxxxxxx LDM (exception return) 0 0 0 0 STMDA, STMED 0 0 0 1 LDMDA, LDMFA 0 1 0 0 STM, STMIA, STMEA A1 0 1 0 1 LDM, LDMIA, LDMFD A1 1 0 0 0 STMDB, STMFD A1 1 0 0 1 LDMDB, LDMEA A1 1 1 0 0 STMIB, STMFA 1 1 0 1 LDMIB, LDMED System register access, Advanced SIMD, floating-point, and Supervisor call != 1111 1 1 1 0 0 0 0 1 0 0 1 (0) (0) 1 (0) (0) (0) (0) Decode fields Instruction page Encoding op 0 VMOV (between general-purpose register and half-precision) From general-purpose register 1 VMOV (between general-purpose register and half-precision) To general-purpose register != 1111 1 1 1 0 0 0 0 1 0 1 0 (0) (0) 1 (0) (0) (0) (0) Decode fields Instruction page Encoding op 0 VMOV (between general-purpose register and single-precision) From general-purpose register 1 VMOV (between general-purpose register and single-precision) To general-purpose register != 1111 1 1 1 0 1 1 1 1 0 1 0 (0) (0) (0) 1 (0) (0) (0) (0) Decode fields Instruction page Encoding L 0 VMSR A1 1 VMRS A1 != 1111 1 1 1 0 1 0 1 1 1 (0) (0) (0) (0) Decode fields Instruction page Encoding opc1 L opc2 1 VMOV (scalar to general-purpose register) A1 0xx 0 VMOV (general-purpose register to scalar) A1 1xx 0 1x UNALLOCATED 1x0 0 0x VDUP (general-purpose register) 64-bit SIMD vector 1x1 0 0x VDUP (general-purpose register) 128-bit SIMD vector != 1111 1 1 1 0 1 1 1 1 Decode fields Instruction page Encoding L 0 MCR A1 1 MRC A1 != 1111 1 1 0 0 0 0 1 0 Decode fields Instruction page Encoding D op size opc2 o3 0 UNALLOCATED 1 0x UNALLOCATED 1 1x 00 0 UNALLOCATED 1 1x != 00 UNALLOCATED 1 0 10 00 1 VMOV (between two general-purpose registers and two single-precision registers) From general-purpose registers 1 0 11 00 1 VMOV (between two general-purpose registers and a doubleword floating-point register) From general-purpose registers 1 1 10 00 1 VMOV (between two general-purpose registers and two single-precision registers) To general-purpose registers 1 1 11 00 1 VMOV (between two general-purpose registers and a doubleword floating-point register) To general-purpose registers != 1111 1 1 0 0 0 0 1 1 1 Decode fields Instruction page Encoding D L 0 UNALLOCATED 1 0 MCRR A1 1 1 MRRC A1 != 1111 1 1 0 1 0 Decode fields Instruction page Encoding P:U:W L Rn size imm8 001 UNALLOCATED 01x 0x UNALLOCATED 01x 0 10 VSTM, VSTMDB, VSTMIA Increment After 01x 0 11 xxxxxxx0 VSTM, VSTMDB, VSTMIA Increment After 01x 0 11 xxxxxxx1 FSTMDBX, FSTMIAX Increment After 01x 1 10 VLDM, VLDMDB, VLDMIA Increment After 01x 1 11 xxxxxxx0 VLDM, VLDMDB, VLDMIA Increment After 01x 1 11 xxxxxxx1 FLDM*X (FLDMDBX, FLDMIAX) Increment After 1x1 0x UNALLOCATED 1x0 00 UNALLOCATED 111 1x UNALLOCATED 1x0 0 01 VSTR Half-precision scalar 101 0 10 VSTM, VSTMDB, VSTMIA Decrement Before 1x0 0 10 VSTR Single-precision scalar 1x0 0 11 VSTR Double-precision scalar 101 0 11 xxxxxxx0 VSTM, VSTMDB, VSTMIA Decrement Before 101 0 11 xxxxxxx1 FSTMDBX, FSTMIAX Decrement Before 101 1 10 VLDM, VLDMDB, VLDMIA Decrement Before 101 1 11 xxxxxxx0 VLDM, VLDMDB, VLDMIA Decrement Before 101 1 11 xxxxxxx1 FLDM*X (FLDMDBX, FLDMIAX) Decrement Before 1x0 1 1111 01 VLDR (literal) Half-precision scalar 1x0 1 1111 10 VLDR (literal) Single-precision scalar 1x0 1 1111 11 VLDR (literal) Double-precision scalar 1x0 1 != 1111 01 VLDR (immediate) Half-precision scalar 1x0 1 != 1111 10 VLDR (immediate) Single-precision scalar 1x0 1 != 1111 11 VLDR (immediate) Double-precision scalar != 1111 1 1 0 1 1 1 Decode fields Instruction page Encoding P:U:W D L Rn CRd cp15 01x 0 00xx UNALLOCATED 001 0 00xx UNALLOCATED 01x 0 0100 UNALLOCATED 001 0 0100 UNALLOCATED 01x 0 0101 1 UNALLOCATED 001 0 0101 1 UNALLOCATED 01x 0 011x UNALLOCATED 001 0 011x UNALLOCATED 01x 0 1xxx UNALLOCATED 001 0 1xxx UNALLOCATED 0x1 0 0 0101 0 STC Post-indexed 010 0 0 0101 0 STC Unindexed 0x1 0 1 != 1111 0101 0 LDC (immediate) Post-indexed 010 0 1 != 1111 0101 0 LDC (immediate) Unindexed 01x 1 UNALLOCATED 001 1 UNALLOCATED 1xx 0 00xx UNALLOCATED 1xx 0 0100 UNALLOCATED 1xx 0 0101 1 UNALLOCATED 1xx 0 011x UNALLOCATED 1xx 0 1xxx UNALLOCATED 1x0 0 0 0101 0 STC Offset 1x1 0 0 0101 0 STC Pre-indexed 1x0 0 1 != 1111 0101 0 LDC (immediate) Offset 1x1 0 1 != 1111 0101 0 LDC (immediate) Pre-indexed 1xx 1 UNALLOCATED != 000 0 1 1111 0101 0 LDC (literal) A1 != 1111 1 1 1 0 1 1 1 1 0 1 0 Decode fields Instruction page Encoding o1 opc2 size o3 00 UNALLOCATED 0 000 01 0 UNALLOCATED 0 000 01 1 VABS Half-precision scalar 0 000 10 0 VMOV (register) Single-precision scalar 0 000 10 1 VABS Single-precision scalar 0 000 11 0 VMOV (register) Double-precision scalar 0 000 11 1 VABS Double-precision scalar 0 001 01 0 VNEG Half-precision scalar 0 001 01 1 VSQRT Half-precision scalar 0 001 10 0 VNEG Single-precision scalar 0 001 10 1 VSQRT Single-precision scalar 0 001 11 0 VNEG Double-precision scalar 0 001 11 1 VSQRT Double-precision scalar 0 010 01 UNALLOCATED 0 010 10 0 VCVTB Half-precision to single-precision 0 010 10 1 VCVTT Half-precision to single-precision 0 010 11 0 VCVTB Half-precision to double-precision 0 010 11 1 VCVTT Half-precision to double-precision 0 011 01 0 VCVTB (BFloat16) A1 0 011 01 1 VCVTT (BFloat16) A1 0 011 10 0 VCVTB Single-precision to half-precision 0 011 10 1 VCVTT Single-precision to half-precision 0 011 11 0 VCVTB Double-precision to half-precision 0 011 11 1 VCVTT Double-precision to half-precision 0 100 01 0 VCMP Half-precision scalar 0 100 01 1 VCMPE Half-precision scalar 0 100 10 0 VCMP Single-precision scalar 0 100 10 1 VCMPE Single-precision scalar 0 100 11 0 VCMP Double-precision scalar 0 100 11 1 VCMPE Double-precision scalar 0 101 01 0 VCMP Half-precision scalar 0 101 01 1 VCMPE Half-precision scalar 0 101 10 0 VCMP Single-precision scalar 0 101 10 1 VCMPE Single-precision scalar 0 101 11 0 VCMP Double-precision scalar 0 101 11 1 VCMPE Double-precision scalar 0 110 01 0 VRINTR Half-precision scalar 0 110 01 1 VRINTZ (floating-point) Half-precision scalar 0 110 10 0 VRINTR Single-precision scalar 0 110 10 1 VRINTZ (floating-point) Single-precision scalar 0 110 11 0 VRINTR Double-precision scalar 0 110 11 1 VRINTZ (floating-point) Double-precision scalar 0 111 01 0 VRINTX (floating-point) Half-precision scalar 0 111 01 1 UNALLOCATED 0 111 10 0 VRINTX (floating-point) Single-precision scalar 0 111 10 1 VCVT (between double-precision and single-precision) Single-precision to double-precision 0 111 11 0 VRINTX (floating-point) Double-precision scalar 0 111 11 1 VCVT (between double-precision and single-precision) Double-precision to single-precision 1 000 01 VCVT (integer to floating-point, floating-point) Half-precision scalar 1 000 10 VCVT (integer to floating-point, floating-point) Single-precision scalar 1 000 11 VCVT (integer to floating-point, floating-point) Double-precision scalar 1 001 01 UNALLOCATED 1 001 10 UNALLOCATED 1 001 11 0 UNALLOCATED 1 001 11 1 VJCVT A1 1 01x 01 VCVT (between floating-point and fixed-point, floating-point) Half-precision scalar 1 01x 10 VCVT (between floating-point and fixed-point, floating-point) Single-precision scalar 1 01x 11 VCVT (between floating-point and fixed-point, floating-point) Double-precision scalar 1 100 01 0 VCVTR Half-precision scalar 1 100 01 1 VCVT (floating-point to integer, floating-point) Half-precision scalar 1 100 10 0 VCVTR Single-precision scalar 1 100 10 1 VCVT (floating-point to integer, floating-point) Single-precision scalar 1 100 11 0 VCVTR Double-precision scalar 1 100 11 1 VCVT (floating-point to integer, floating-point) Double-precision scalar 1 101 01 0 VCVTR Half-precision scalar 1 101 01 1 VCVT (floating-point to integer, floating-point) Half-precision scalar 1 101 10 0 VCVTR Single-precision scalar 1 101 10 1 VCVT (floating-point to integer, floating-point) Single-precision scalar 1 101 11 0 VCVTR Double-precision scalar 1 101 11 1 VCVT (floating-point to integer, floating-point) Double-precision scalar 1 11x 01 VCVT (between floating-point and fixed-point, floating-point) Half-precision scalar 1 11x 10 VCVT (between floating-point and fixed-point, floating-point) Single-precision scalar 1 11x 11 VCVT (between floating-point and fixed-point, floating-point) Double-precision scalar != 1111 1 1 1 0 1 1 1 1 0 (0) 0 (0) 0 Decode fields Instruction page Encoding size 00 UNALLOCATED 01 VMOV (immediate) Half-precision scalar 10 VMOV (immediate) Single-precision scalar 11 VMOV (immediate) Double-precision scalar != 1111 1 1 1 0 1 0 0 Decode fields Instruction page Encoding o0:o1 size o2 0xx 00 UNALLOCATED 000 01 0 VMLA (floating-point) Half-precision scalar 001 01 0 VNMLS Half-precision scalar 010 01 0 VMUL (floating-point) Half-precision scalar 011 01 0 VADD (floating-point) Half-precision scalar 000 01 1 VMLS (floating-point) Half-precision scalar 001 01 1 VNMLA Half-precision scalar 010 01 1 VNMUL Half-precision scalar 011 01 1 VSUB (floating-point) Half-precision scalar 000 10 0 VMLA (floating-point) Single-precision scalar 001 10 0 VNMLS Single-precision scalar 010 10 0 VMUL (floating-point) Single-precision scalar 011 10 0 VADD (floating-point) Single-precision scalar 000 10 1 VMLS (floating-point) Single-precision scalar 001 10 1 VNMLA Single-precision scalar 010 10 1 VNMUL Single-precision scalar 011 10 1 VSUB (floating-point) Single-precision scalar 000 11 0 VMLA (floating-point) Double-precision scalar 001 11 0 VNMLS Double-precision scalar 010 11 0 VMUL (floating-point) Double-precision scalar 011 11 0 VADD (floating-point) Double-precision scalar 000 11 1 VMLS (floating-point) Double-precision scalar 001 11 1 VNMLA Double-precision scalar 010 11 1 VNMUL Double-precision scalar 011 11 1 VSUB (floating-point) Double-precision scalar 100 x1 1 UNALLOCATED 10x 00 UNALLOCATED 110 00 UNALLOCATED 100 01 0 VDIV Half-precision scalar 101 01 0 VFNMS Half-precision scalar 110 01 0 VFMA Half-precision scalar 101 01 1 VFNMA Half-precision scalar 110 01 1 VFMS Half-precision scalar 100 10 0 VDIV Single-precision scalar 101 10 0 VFNMS Single-precision scalar 110 10 0 VFMA Single-precision scalar 100 10 1 UNALLOCATED 101 10 1 VFNMA Single-precision scalar 110 10 1 VFMS Single-precision scalar 100 11 0 VDIV Double-precision scalar 101 11 0 VFNMS Double-precision scalar 110 11 0 VFMA Double-precision scalar 101 11 1 VFNMA Double-precision scalar 110 11 1 VFMS Double-precision scalar != 1111 1 1 1 1 Instruction page Encoding SVC A1 1 1 1 1 1 1 0 1 0 Decode fields Instruction page Encoding op1 op2 op3 op4 Q U 0 1 0 UNALLOCATED 1x 0 0 0 0 VCMLA 64-bit SIMD vector 1x 0 0 1 0 VCMLA 128-bit SIMD vector x0 0x 0 0 0 UNALLOCATED x1 0x 0 0 0 0 VCADD 64-bit SIMD vector x1 0x 0 0 1 0 VCADD 128-bit SIMD vector 0x x1 1 0 UNALLOCATED 0x 0x 1 UNALLOCATED 0x 1x 0 1 1 UNALLOCATED 0x 10 1 0 0 0 UNALLOCATED 0x 11 1 1 UNALLOCATED 00 00 1 0 0 0 UNALLOCATED 00 00 1 0 1 0 VMMLA A1 00 00 1 1 0 0 VDOT (vector) 64-bit SIMD vector 00 00 1 1 1 0 VDOT (vector) 128-bit SIMD vector 00 10 0 0 0 1 VFMAL (vector) 64-bit SIMD vector 00 10 0 0 1 1 VFMAL (vector) 128-bit SIMD vector 00 10 1 0 0 1 UNALLOCATED 00 10 1 0 1 0 VSMMLA A1 00 10 1 0 1 1 VUMMLA A1 00 10 1 1 0 0 VSDOT (vector) 64-bit SIMD vector 00 10 1 1 0 1 VUDOT (vector) 64-bit SIMD vector 00 10 1 1 1 0 VSDOT (vector) 128-bit SIMD vector 00 10 1 1 1 1 VUDOT (vector) 128-bit SIMD vector 00 11 0 0 1 VFMAB, VFMAT (BFloat16, vector) A1 01 00 1 0 UNALLOCATED 01 10 0 0 0 1 VFMSL (vector) 64-bit SIMD vector 01 10 0 0 1 1 VFMSL (vector) 128-bit SIMD vector 01 10 1 1 UNALLOCATED 01 10 1 0 1 0 VUSMMLA A1 01 10 1 1 0 0 VUSDOT (vector) 64-bit SIMD vector 01 10 1 1 1 0 VUSDOT (vector) 128-bit SIMD vector 01 11 0 0 1 UNALLOCATED 1x 0 1 UNALLOCATED 1x 1 UNALLOCATED 1 1 1 1 1 1 1 0 0 1 0 != 00 0 0 Decode fields Instruction page Encoding cc size 00 01 VSELEQ, VSELGE, VSELGT, VSELVS Equal, half-precision scalar 00 10 VSELEQ, VSELGE, VSELGT, VSELVS Equal, single-precision scalar 00 11 VSELEQ, VSELGE, VSELGT, VSELVS Equal, double-precision scalar 01 01 VSELEQ, VSELGE, VSELGT, VSELVS Unordered, half-precision scalar 01 10 VSELEQ, VSELGE, VSELGT, VSELVS Unordered, single-precision scalar 01 11 VSELEQ, VSELGE, VSELGT, VSELVS Unordered, double-precision scalar 10 01 VSELEQ, VSELGE, VSELGT, VSELVS Greater than or Equal, half-precision scalar 10 10 VSELEQ, VSELGE, VSELGT, VSELVS Greater than or Equal, single-precision scalar 10 11 VSELEQ, VSELGE, VSELGT, VSELVS Greater than or Equal, double-precision scalar 11 01 VSELEQ, VSELGE, VSELGT, VSELVS Greater than, half-precision scalar 11 10 VSELEQ, VSELGE, VSELGT, VSELVS Greater than, single-precision scalar 11 11 VSELEQ, VSELGE, VSELGT, VSELVS Greater than, double-precision scalar 1 1 1 1 1 1 1 0 1 0 0 1 0 != 00 0 Decode fields Instruction page Encoding size op 01 0 VMAXNM Half-precision scalar 01 1 VMINNM Half-precision scalar 10 0 VMAXNM Single-precision scalar 10 1 VMINNM Single-precision scalar 11 0 VMAXNM Double-precision scalar 11 1 VMINNM Double-precision scalar 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0 1 0 != 00 1 0 Decode fields Instruction page Encoding size op 01 UNALLOCATED 10 0 VMOVX A1 10 1 VINS A1 11 UNALLOCATED 1 1 1 1 1 1 1 0 1 1 1 1 1 0 != 00 1 0 Decode fields Instruction page Encoding op1 RM size op 0 != 00 1 UNALLOCATED 0 00 01 0 VRINTA (floating-point) Half-precision scalar 0 00 10 0 VRINTA (floating-point) Single-precision scalar 0 00 11 0 VRINTA (floating-point) Double-precision scalar 0 01 01 0 VRINTN (floating-point) Half-precision scalar 0 01 10 0 VRINTN (floating-point) Single-precision scalar 0 01 11 0 VRINTN (floating-point) Double-precision scalar 0 10 01 0 VRINTP (floating-point) Half-precision scalar 0 10 10 0 VRINTP (floating-point) Single-precision scalar 0 10 11 0 VRINTP (floating-point) Double-precision scalar 0 11 01 0 VRINTM (floating-point) Half-precision scalar 0 11 10 0 VRINTM (floating-point) Single-precision scalar 0 11 11 0 VRINTM (floating-point) Double-precision scalar 1 00 01 VCVTA (floating-point) Half-precision scalar 1 00 10 VCVTA (floating-point) Single-precision scalar 1 00 11 VCVTA (floating-point) Double-precision scalar 1 01 01 VCVTN (floating-point) Half-precision scalar 1 01 10 VCVTN (floating-point) Single-precision scalar 1 01 11 VCVTN (floating-point) Double-precision scalar 1 10 01 VCVTP (floating-point) Half-precision scalar 1 10 10 VCVTP (floating-point) Single-precision scalar 1 10 11 VCVTP (floating-point) Double-precision scalar 1 11 01 VCVTM (floating-point) Half-precision scalar 1 11 10 VCVTM (floating-point) Single-precision scalar 1 11 11 VCVTM (floating-point) Double-precision scalar 1 1 1 1 1 1 1 0 1 0 0 0 Decode fields Instruction page Encoding op1 op2 Q U 0 0 0 VCMLA (by element) 64-bit SIMD vector of half-precision floating-point 0 1 0 VCMLA (by element) 128-bit SIMD vector of half-precision floating-point 0 00 0 1 VFMAL (by scalar) 64-bit SIMD vector 0 00 1 1 VFMAL (by scalar) 128-bit SIMD vector 0 01 0 1 VFMSL (by scalar) 64-bit SIMD vector 0 01 1 1 VFMSL (by scalar) 128-bit SIMD vector 0 10 1 UNALLOCATED 0 11 1 VFMAB, VFMAT (BFloat16, by scalar) A1 1 1 UNALLOCATED 1 0 0 VCMLA (by element) 64-bit SIMD vector of single-precision floating-point 1 1 0 VCMLA (by element) 128-bit SIMD vector of single-precision floating-point 1 1 1 1 1 1 1 0 1 1 0 Decode fields Instruction page Encoding op1 op2 op4 Q U x0 0 UNALLOCATED x1 UNALLOCATED 0 00 1 1 UNALLOCATED 0 00 1 0 0 VDOT (by element) 64-bit SIMD vector 0 00 1 1 0 VDOT (by element) 128-bit SIMD vector 0 10 1 0 0 VSDOT (by element) 64-bit SIMD vector 0 10 1 0 1 VUDOT (by element) 64-bit SIMD vector 0 10 1 1 0 VSDOT (by element) 128-bit SIMD vector 0 10 1 1 1 VUDOT (by element) 128-bit SIMD vector 1 00 1 0 0 VUSDOT (by element) 64-bit SIMD vector 1 00 1 0 1 VSUDOT (by element) 64-bit SIMD vector 1 00 1 1 0 VUSDOT (by element) 128-bit SIMD vector 1 00 1 1 1 VSUDOT (by element) 128-bit SIMD vector 1 10 1 UNALLOCATED Unconditional instructions 1 1 1 1 0 0 1 0 Decode fields Instruction page Encoding U size opc Q o1 0000 0 0 VHADD 64-bit SIMD vector 0000 0 1 VQADD 64-bit SIMD vector 0000 1 0 VHADD 128-bit SIMD vector 0000 1 1 VQADD 128-bit SIMD vector 0001 0 0 VRHADD 64-bit SIMD vector 0001 1 0 VRHADD 128-bit SIMD vector 0010 0 0 VHSUB 64-bit SIMD vector 0010 0 1 VQSUB 64-bit SIMD vector 0010 1 0 VHSUB 128-bit SIMD vector 0010 1 1 VQSUB 128-bit SIMD vector 0011 0 0 VCGT (register) 64-bit SIMD vector 0011 0 1 VCGE (register) 64-bit SIMD vector 0011 1 0 VCGT (register) 128-bit SIMD vector 0011 1 1 VCGE (register) 128-bit SIMD vector 0100 0 0 VSHL (register) 64-bit SIMD vector 0100 0 1 VQSHL (register) 64-bit SIMD vector 0100 1 0 VSHL (register) 128-bit SIMD vector 0100 1 1 VQSHL (register) 128-bit SIMD vector 0101 0 0 VRSHL 64-bit SIMD vector 0101 0 1 VQRSHL 64-bit SIMD vector 0101 1 0 VRSHL 128-bit SIMD vector 0101 1 1 VQRSHL 128-bit SIMD vector 0110 0 0 VMAX (integer) 64-bit SIMD vector 0110 0 1 VMIN (integer) 64-bit SIMD vector 0110 1 0 VMAX (integer) 128-bit SIMD vector 0110 1 1 VMIN (integer) 128-bit SIMD vector 0111 0 0 VABD (integer) 64-bit SIMD vector 0111 0 1 VABA 64-bit SIMD vector 0111 1 0 VABD (integer) 128-bit SIMD vector 0111 1 1 VABA 128-bit SIMD vector 1001 0 1 VMUL (integer and polynomial) 64-bit SIMD vector 1001 1 1 VMUL (integer and polynomial) 128-bit SIMD vector 1010 0 0 VPMAX (integer) A1 1010 0 1 VPMIN (integer) A1 1010 1 UNALLOCATED 0 1000 0 0 VADD (integer) 64-bit SIMD vector 0 1000 0 1 VTST 64-bit SIMD vector 0 1000 1 0 VADD (integer) 128-bit SIMD vector 0 1000 1 1 VTST 128-bit SIMD vector 0 1001 0 0 VMLA (integer) 64-bit SIMD vector 0 1001 1 0 VMLA (integer) 128-bit SIMD vector 0 1011 1 VPADD (integer) A1 0 1011 0 0 VQDMULH 64-bit SIMD vector 0 1011 1 0 VQDMULH 128-bit SIMD vector 0 0x 1100 0 1 VFMA 64-bit SIMD vector 0 0x 1100 1 1 VFMA 128-bit SIMD vector 0 0x 1101 0 0 VADD (floating-point) 64-bit SIMD vector 0 0x 1101 0 1 VMLA (floating-point) 64-bit SIMD vector 0 0x 1101 1 0 VADD (floating-point) 128-bit SIMD vector 0 0x 1101 1 1 VMLA (floating-point) 128-bit SIMD vector 0 0x 1110 1 UNALLOCATED 0 0x 1110 0 0 VCEQ (register) 64-bit SIMD vector 0 0x 1110 1 0 VCEQ (register) 128-bit SIMD vector 0 0x 1111 0 0 VMAX (floating-point) 64-bit SIMD vector 0 0x 1111 0 1 VRECPS 64-bit SIMD vector 0 0x 1111 1 0 VMAX (floating-point) 128-bit SIMD vector 0 0x 1111 1 1 VRECPS 128-bit SIMD vector 0 00 0001 0 1 VAND (register) 64-bit SIMD vector 0 00 0001 1 1 VAND (register) 128-bit SIMD vector 0 00 1100 0 SHA1C A1 0 01 0001 0 1 VBIC (register) 64-bit SIMD vector 0 01 0001 1 1 VBIC (register) 128-bit SIMD vector 0 01 1100 0 SHA1P A1 0 1x 1100 0 1 VFMS 64-bit SIMD vector 0 1x 1100 1 1 VFMS 128-bit SIMD vector 0 1x 1101 0 0 VSUB (floating-point) 64-bit SIMD vector 0 1x 1101 0 1 VMLS (floating-point) 64-bit SIMD vector 0 1x 1101 1 0 VSUB (floating-point) 128-bit SIMD vector 0 1x 1101 1 1 VMLS (floating-point) 128-bit SIMD vector 0 1x 1110 UNALLOCATED 0 1x 1111 0 0 VMIN (floating-point) 64-bit SIMD vector 0 1x 1111 0 1 VRSQRTS 64-bit SIMD vector 0 1x 1111 1 0 VMIN (floating-point) 128-bit SIMD vector 0 1x 1111 1 1 VRSQRTS 128-bit SIMD vector 0 10 0001 0 1 VORR (register) 64-bit SIMD vector 0 10 0001 1 1 VORR (register) 128-bit SIMD vector 0 10 1100 0 SHA1M A1 0 11 0001 0 1 VORN (register) 64-bit SIMD vector 0 11 0001 1 1 VORN (register) 128-bit SIMD vector 0 11 1100 0 SHA1SU0 A1 1 1000 0 0 VSUB (integer) 64-bit SIMD vector 1 1000 0 1 VCEQ (register) 64-bit SIMD vector 1 1000 1 0 VSUB (integer) 128-bit SIMD vector 1 1000 1 1 VCEQ (register) 128-bit SIMD vector 1 1001 0 0 VMLS (integer) 64-bit SIMD vector 1 1001 1 0 VMLS (integer) 128-bit SIMD vector 1 1011 0 0 VQRDMULH 64-bit SIMD vector 1 1011 0 1 VQRDMLAH 64-bit SIMD vector 1 1011 1 0 VQRDMULH 128-bit SIMD vector 1 1011 1 1 VQRDMLAH 128-bit SIMD vector 1 1100 0 1 VQRDMLSH 64-bit SIMD vector 1 1100 1 1 VQRDMLSH 128-bit SIMD vector 1 1111 1 0 UNALLOCATED 1 0x 1101 0 VPADD (floating-point) A1 1 0x 1101 0 1 VMUL (floating-point) 64-bit SIMD vector 1 0x 1101 1 1 VMUL (floating-point) 128-bit SIMD vector 1 0x 1110 0 0 VCGE (register) 64-bit SIMD vector 1 0x 1110 0 1 VACGE 64-bit SIMD vector 1 0x 1110 1 0 VCGE (register) 128-bit SIMD vector 1 0x 1110 1 1 VACGE 128-bit SIMD vector 1 0x 1111 0 0 VPMAX (floating-point) A1 1 0x 1111 0 1 VMAXNM 64-bit SIMD vector 1 0x 1111 1 1 VMAXNM 128-bit SIMD vector 1 00 0001 0 1 VEOR 64-bit SIMD vector 1 00 0001 1 1 VEOR 128-bit SIMD vector 1 00 1100 0 SHA256H A1 1 01 0001 0 1 VBSL 64-bit SIMD vector 1 01 0001 1 1 VBSL 128-bit SIMD vector 1 01 1100 0 SHA256H2 A1 1 1x 1101 1 UNALLOCATED 1 1x 1101 0 0 VABD (floating-point) 64-bit SIMD vector 1 1x 1101 1 0 VABD (floating-point) 128-bit SIMD vector 1 1x 1110 0 0 VCGT (register) 64-bit SIMD vector 1 1x 1110 0 1 VACGT 64-bit SIMD vector 1 1x 1110 1 0 VCGT (register) 128-bit SIMD vector 1 1x 1110 1 1 VACGT 128-bit SIMD vector 1 1x 1111 0 0 VPMIN (floating-point) A1 1 1x 1111 0 1 VMINNM 64-bit SIMD vector 1 1x 1111 1 1 VMINNM 128-bit SIMD vector 1 10 0001 0 1 VBIT 64-bit SIMD vector 1 10 0001 1 1 VBIT 128-bit SIMD vector 1 10 1100 0 SHA256SU1 A1 1 11 0001 0 1 VBIF 64-bit SIMD vector 1 11 0001 1 1 VBIF 128-bit SIMD vector 1 11 1100 0 UNALLOCATED 1 1 1 1 0 0 1 0 1 1 1 0 Decode fields Instruction page Encoding Q 0 VEXT (byte elements) 64-bit SIMD vector 1 VEXT (byte elements) 128-bit SIMD vector 1 1 1 1 0 0 1 1 1 1 1 0 0 Decode fields Instruction page Encoding size opc1 opc2 Q 00 0000 0 VREV64 64-bit SIMD vector 00 0000 1 VREV64 128-bit SIMD vector 00 0001 0 VREV32 64-bit SIMD vector 00 0001 1 VREV32 128-bit SIMD vector 00 0010 0 VREV16 64-bit SIMD vector 00 0010 1 VREV16 128-bit SIMD vector 00 0011 UNALLOCATED 00 010x 0 VPADDL 64-bit SIMD vector 00 010x 1 VPADDL 128-bit SIMD vector 00 0110 0 AESE A1 00 0110 1 AESD A1 00 0111 0 AESMC A1 00 0111 1 AESIMC A1 00 1000 0 VCLS 64-bit SIMD vector 00 1000 1 VCLS 128-bit SIMD vector 00 1001 0 VCLZ 64-bit SIMD vector 00 1001 1 VCLZ 128-bit SIMD vector 00 1010 0 VCNT 64-bit SIMD vector 00 1010 1 VCNT 128-bit SIMD vector 00 1011 0 VMVN (register) 64-bit SIMD vector 00 1011 1 VMVN (register) 128-bit SIMD vector 00 110x 0 VPADAL 64-bit SIMD vector 00 110x 1 VPADAL 128-bit SIMD vector 00 1110 0 VQABS 64-bit SIMD vector 00 1110 1 VQABS 128-bit SIMD vector 00 1111 0 VQNEG 64-bit SIMD vector 00 1111 1 VQNEG 128-bit SIMD vector 01 x000 0 VCGT (immediate #0) 64-bit SIMD vector 01 x000 1 VCGT (immediate #0) 128-bit SIMD vector 01 x001 0 VCGE (immediate #0) 64-bit SIMD vector 01 x001 1 VCGE (immediate #0) 128-bit SIMD vector 01 x010 0 VCEQ (immediate #0) 64-bit SIMD vector 01 x010 1 VCEQ (immediate #0) 128-bit SIMD vector 01 x011 0 VCLE (immediate #0) 64-bit SIMD vector 01 x011 1 VCLE (immediate #0) 128-bit SIMD vector 01 x100 0 VCLT (immediate #0) 64-bit SIMD vector 01 x100 1 VCLT (immediate #0) 128-bit SIMD vector 01 x110 0 VABS 64-bit SIMD vector 01 x110 1 VABS 128-bit SIMD vector 01 x111 0 VNEG 64-bit SIMD vector 01 x111 1 VNEG 128-bit SIMD vector 01 0101 0 UNALLOCATED 01 0101 1 SHA1H A1 01 1101 UNALLOCATED 10 x110 1 UNALLOCATED 10 0001 0 VTRN 64-bit SIMD vector 10 0001 1 VTRN 128-bit SIMD vector 10 0010 0 VUZP 64-bit SIMD vector 10 0010 1 VUZP 128-bit SIMD vector 10 0011 0 VZIP 64-bit SIMD vector 10 0011 1 VZIP 128-bit SIMD vector 10 0100 0 VMOVN A1 10 0100 1 VQMOVN, VQMOVUN Unsigned result 10 0101 VQMOVN, VQMOVUN Signed result 10 0110 0 VSHLL A2 10 0111 0 SHA1SU1 A1 10 0111 1 SHA256SU0 A1 10 1000 0 VRINTN (Advanced SIMD) 64-bit SIMD vector 10 1000 1 VRINTN (Advanced SIMD) 128-bit SIMD vector 10 1001 0 VRINTX (Advanced SIMD) 64-bit SIMD vector 10 1001 1 VRINTX (Advanced SIMD) 128-bit SIMD vector 10 1010 0 VRINTA (Advanced SIMD) 64-bit SIMD vector 10 1010 1 VRINTA (Advanced SIMD) 128-bit SIMD vector 10 1011 0 VRINTZ (Advanced SIMD) 64-bit SIMD vector 10 1011 1 VRINTZ (Advanced SIMD) 128-bit SIMD vector 10 1100 0 VCVT (between half-precision and single-precision, Advanced SIMD) Single-precision to half-precision 10 1101 0 VRINTM (Advanced SIMD) 64-bit SIMD vector 10 1101 1 VRINTM (Advanced SIMD) 128-bit SIMD vector 10 1110 0 VCVT (between half-precision and single-precision, Advanced SIMD) Half-precision to single-precision 10 1111 0 VRINTP (Advanced SIMD) 64-bit SIMD vector 10 1111 1 VRINTP (Advanced SIMD) 128-bit SIMD vector 11 000x 0 VCVTA (Advanced SIMD) 64-bit SIMD vector 11 000x 1 VCVTA (Advanced SIMD) 128-bit SIMD vector 11 001x 0 VCVTN (Advanced SIMD) 64-bit SIMD vector 11 001x 1 VCVTN (Advanced SIMD) 128-bit SIMD vector 11 010x 0 VCVTP (Advanced SIMD) 64-bit SIMD vector 11 010x 1 VCVTP (Advanced SIMD) 128-bit SIMD vector 11 011x 0 VCVTM (Advanced SIMD) 64-bit SIMD vector 11 011x 1 VCVTM (Advanced SIMD) 128-bit SIMD vector 11 10x0 0 VRECPE 64-bit SIMD vector 11 10x0 1 VRECPE 128-bit SIMD vector 11 10x1 0 VRSQRTE 64-bit SIMD vector 11 10x1 1 VRSQRTE 128-bit SIMD vector 11 11xx 0 VCVT (between floating-point and integer, Advanced SIMD) 64-bit SIMD vector 11 11xx 1 VCVT (between floating-point and integer, Advanced SIMD) 128-bit SIMD vector 00 10 0000 0 VSWP 64-bit SIMD vector 00 10 0000 1 VSWP 128-bit SIMD vector 01 10 1100 1 VCVT (from single-precision to BFloat16, Advanced SIMD) A1 != 00 10 0000 UNALLOCATED != 01 10 1100 1 UNALLOCATED 1 1 1 1 0 0 1 1 1 1 1 1 0 0 Decode fields Instruction page Encoding op 0 VTBL, VTBX VTBL 1 VTBL, VTBX VTBX 1 1 1 1 0 0 1 1 1 1 1 1 1 0 Decode fields Instruction page Encoding opc Q 000 0 VDUP (scalar) 000 1 VDUP (scalar) != 000 UNALLOCATED 1 1 1 1 0 0 1 1 != 11 0 0 Decode fields Instruction page Encoding U opc 0000 VADDL A1 0001 VADDW A1 0010 VSUBL A1 0011 VSUBW A1 0101 VABAL A1 0111 VABDL (integer) A1 1000 VMLAL (integer) A1 1010 VMLSL (integer) A1 11x0 VMULL (integer and polynomial) A1 0 0100 VADDHN A1 0 0110 VSUBHN A1 0 1001 VQDMLAL A1 0 1011 VQDMLSL A1 0 1101 VQDMULL A1 0 1111 UNALLOCATED 1 0100 VRADDHN A1 1 0110 VRSUBHN A1 1 1xx1 UNALLOCATED 1 1 1 1 0 0 1 1 != 11 1 0 Decode fields Instruction page Encoding Q size opc != 11 0010 VMLAL (by scalar) A1 != 11 0110 VMLSL (by scalar) A1 != 11 1010 VMULL (by scalar) A1 0 != 11 000x VMLA (by scalar) 64-bit SIMD vector 0 != 11 0011 VQDMLAL A2 0 != 11 010x VMLS (by scalar) 64-bit SIMD vector 0 != 11 0111 VQDMLSL A2 0 != 11 100x VMUL (by scalar) 64-bit SIMD vector 0 != 11 1011 VQDMULL A2 0 != 11 1100 VQDMULH 64-bit SIMD vector 0 != 11 1101 VQRDMULH 64-bit SIMD vector 0 != 11 1110 VQRDMLAH 64-bit SIMD vector 0 != 11 1111 VQRDMLSH 64-bit SIMD vector 1 != 11 0x11 UNALLOCATED 1 != 11 000x VMLA (by scalar) 128-bit SIMD vector 1 != 11 010x VMLS (by scalar) 128-bit SIMD vector 1 != 11 100x VMUL (by scalar) 128-bit SIMD vector 1 != 11 1011 UNALLOCATED 1 != 11 1100 VQDMULH 128-bit SIMD vector 1 != 11 1101 VQRDMULH 128-bit SIMD vector 1 != 11 1110 VQRDMLAH 128-bit SIMD vector 1 != 11 1111 VQRDMLSH 128-bit SIMD vector 1 1 1 1 0 0 1 1 0 0 0 0 1 Decode fields Instruction page Encoding cmode Q op 0xx0 0 0 VMOV (immediate) 64-bit SIMD vector 0xx0 0 1 VMVN (immediate) 64-bit SIMD vector 0xx0 1 0 VMOV (immediate) 128-bit SIMD vector 0xx0 1 1 VMVN (immediate) 128-bit SIMD vector 0xx1 0 0 VORR (immediate) 64-bit SIMD vector 0xx1 0 1 VBIC (immediate) 64-bit SIMD vector 0xx1 1 0 VORR (immediate) 128-bit SIMD vector 0xx1 1 1 VBIC (immediate) 128-bit SIMD vector 10x0 0 0 VMOV (immediate) 64-bit SIMD vector 10x0 0 1 VMVN (immediate) 64-bit SIMD vector 10x0 1 0 VMOV (immediate) 128-bit SIMD vector 10x0 1 1 VMVN (immediate) 128-bit SIMD vector 10x1 0 0 VORR (immediate) 64-bit SIMD vector 10x1 0 1 VBIC (immediate) 64-bit SIMD vector 10x1 1 0 VORR (immediate) 128-bit SIMD vector 10x1 1 1 VBIC (immediate) 128-bit SIMD vector 11xx 0 0 VMOV (immediate) 64-bit SIMD vector 11xx 1 0 VMOV (immediate) 128-bit SIMD vector 110x 0 1 VMVN (immediate) 64-bit SIMD vector 110x 1 1 VMVN (immediate) 128-bit SIMD vector 1110 0 1 VMOV (immediate) 64-bit SIMD vector 1110 1 1 VMOV (immediate) 128-bit SIMD vector 1111 1 UNALLOCATED 1 1 1 1 0 0 1 1 1 Decode fields Instruction page Encoding U imm3H:L imm3L opc Q xxx1 1xxx UNALLOCATED xx10 1010 1 UNALLOCATED xx10 1011 UNALLOCATED x100 1010 1 UNALLOCATED x100 1011 UNALLOCATED 1000 1010 1 UNALLOCATED 1000 1011 UNALLOCATED != 0000 0000 0 VSHR 64-bit SIMD vector != 0000 0000 1 VSHR 128-bit SIMD vector != 0000 0001 0 VSRA 64-bit SIMD vector != 0000 0001 1 VSRA 128-bit SIMD vector != 0000 0010 0 VRSHR 64-bit SIMD vector != 0000 0010 1 VRSHR 128-bit SIMD vector != 0000 0011 0 VRSRA 64-bit SIMD vector != 0000 0011 1 VRSRA 128-bit SIMD vector != 0000 0111 0 VQSHL, VQSHLU (immediate) 64-bit SIMD vector, signed result != 0000 0111 1 VQSHL, VQSHLU (immediate) 128-bit SIMD vector, signed result != 0000 1001 0 VQSHRN, VQSHRUN Signed result != 0000 1001 1 VQRSHRN, VQRSHRUN Signed result != 0000 1010 0 VSHLL A1 != 0000 11xx 0 VCVT (between floating-point and fixed-point, Advanced SIMD) 64-bit SIMD vector != 0000 11xx 1 VCVT (between floating-point and fixed-point, Advanced SIMD) 128-bit SIMD vector != 0000 000 1010 0 VMOVL A1 0 0001 01x0 UNALLOCATED 0 001x 01x0 UNALLOCATED 0 01xx 01x0 UNALLOCATED 0 1xxx 01x0 UNALLOCATED 0 != 0000 0101 0 VSHL (immediate) 64-bit SIMD vector 0 != 0000 0101 1 VSHL (immediate) 128-bit SIMD vector 0 != 0000 1000 0 VSHRN A1 0 != 0000 1000 1 VRSHRN A1 1 != 0000 0100 0 VSRI 64-bit SIMD vector 1 != 0000 0100 1 VSRI 128-bit SIMD vector 1 != 0000 0101 0 VSLI 64-bit SIMD vector 1 != 0000 0101 1 VSLI 128-bit SIMD vector 1 != 0000 0110 0 VQSHL, VQSHLU (immediate) 64-bit SIMD vector, unsigned result 1 != 0000 0110 1 VQSHL, VQSHLU (immediate) 128-bit SIMD vector, unsigned result 1 != 0000 1000 0 VQSHRN, VQSHRUN Unsigned result 1 != 0000 1000 1 VQRSHRN, VQRSHRUN Unsigned result 1 1 1 1 0 1 0 0 0 0 Decode fields Instruction page Encoding L itype Rm 1011 UNALLOCATED 11xx UNALLOCATED 0 000x 1101 VST4 (multiple 4-element structures) Post-indexed 0 000x 1111 VST4 (multiple 4-element structures) Offset 0 000x != 11x1 VST4 (multiple 4-element structures) Post-indexed 0 0010 1101 VST1 (multiple single elements) Post-indexed 0 0010 1111 VST1 (multiple single elements) Offset 0 0010 != 11x1 VST1 (multiple single elements) Post-indexed 0 0011 1101 VST2 (multiple 2-element structures) Post-indexed 0 0011 1111 VST2 (multiple 2-element structures) Offset 0 0011 != 11x1 VST2 (multiple 2-element structures) Post-indexed 0 010x 1101 VST3 (multiple 3-element structures) Post-indexed 0 010x 1111 VST3 (multiple 3-element structures) Offset 0 010x != 11x1 VST3 (multiple 3-element structures) Post-indexed 0 0110 1101 VST1 (multiple single elements) Post-indexed 0 0110 1111 VST1 (multiple single elements) Offset 0 0110 != 11x1 VST1 (multiple single elements) Post-indexed 0 0111 1101 VST1 (multiple single elements) Post-indexed 0 0111 1111 VST1 (multiple single elements) Offset 0 0111 != 11x1 VST1 (multiple single elements) Post-indexed 0 100x 1101 VST2 (multiple 2-element structures) Post-indexed 0 100x 1111 VST2 (multiple 2-element structures) Offset 0 100x != 11x1 VST2 (multiple 2-element structures) Post-indexed 0 1010 1101 VST1 (multiple single elements) Post-indexed 0 1010 1111 VST1 (multiple single elements) Offset 0 1010 != 11x1 VST1 (multiple single elements) Post-indexed 1 000x 1101 VLD4 (multiple 4-element structures) Post-indexed 1 000x 1111 VLD4 (multiple 4-element structures) Offset 1 000x != 11x1 VLD4 (multiple 4-element structures) Post-indexed 1 0010 1101 VLD1 (multiple single elements) Post-indexed 1 0010 1111 VLD1 (multiple single elements) Offset 1 0010 != 11x1 VLD1 (multiple single elements) Post-indexed 1 0011 1101 VLD2 (multiple 2-element structures) Post-indexed 1 0011 1111 VLD2 (multiple 2-element structures) Offset 1 0011 != 11x1 VLD2 (multiple 2-element structures) Post-indexed 1 010x 1101 VLD3 (multiple 3-element structures) Post-indexed 1 010x 1111 VLD3 (multiple 3-element structures) Offset 1 010x != 11x1 VLD3 (multiple 3-element structures) Post-indexed 1 0110 1101 VLD1 (multiple single elements) Post-indexed 1 0110 1111 VLD1 (multiple single elements) Offset 1 0110 != 11x1 VLD1 (multiple single elements) Post-indexed 1 0111 1101 VLD1 (multiple single elements) Post-indexed 1 0111 1111 VLD1 (multiple single elements) Offset 1 0111 != 11x1 VLD1 (multiple single elements) Post-indexed 1 100x 1101 VLD2 (multiple 2-element structures) Post-indexed 1 100x 1111 VLD2 (multiple 2-element structures) Offset 1 100x != 11x1 VLD2 (multiple 2-element structures) Post-indexed 1 1010 1101 VLD1 (multiple single elements) Post-indexed 1 1010 1111 VLD1 (multiple single elements) Offset 1 1010 != 11x1 VLD1 (multiple single elements) Post-indexed 1 1 1 1 0 1 0 0 1 0 1 1 Decode fields Instruction page Encoding L N a Rm 0 UNALLOCATED 1 00 1101 VLD1 (single element to all lanes) Post-indexed 1 00 1111 VLD1 (single element to all lanes) Offset 1 00 != 11x1 VLD1 (single element to all lanes) Post-indexed 1 01 1101 VLD2 (single 2-element structure to all lanes) Post-indexed 1 01 1111 VLD2 (single 2-element structure to all lanes) Offset 1 01 != 11x1 VLD2 (single 2-element structure to all lanes) Post-indexed 1 10 0 1101 VLD3 (single 3-element structure to all lanes) Post-indexed 1 10 0 1111 VLD3 (single 3-element structure to all lanes) Offset 1 10 0 != 11x1 VLD3 (single 3-element structure to all lanes) Post-indexed 1 10 1 UNALLOCATED 1 11 1101 VLD4 (single 4-element structure to all lanes) Post-indexed 1 11 1111 VLD4 (single 4-element structure to all lanes) Offset 1 11 != 11x1 VLD4 (single 4-element structure to all lanes) Post-indexed 1 1 1 1 0 1 0 0 1 0 != 11 Decode fields Instruction page Encoding L size N Rm 0 00 00 1101 VST1 (single element from one lane) Post-indexed 0 00 00 1111 VST1 (single element from one lane) Offset 0 00 00 != 11x1 VST1 (single element from one lane) Post-indexed 0 00 01 1101 VST2 (single 2-element structure from one lane) Post-indexed 0 00 01 1111 VST2 (single 2-element structure from one lane) Offset 0 00 01 != 11x1 VST2 (single 2-element structure from one lane) Post-indexed 0 00 10 1101 VST3 (single 3-element structure from one lane) Post-indexed 0 00 10 1111 VST3 (single 3-element structure from one lane) Offset 0 00 10 != 11x1 VST3 (single 3-element structure from one lane) Post-indexed 0 00 11 1101 VST4 (single 4-element structure from one lane) Post-indexed 0 00 11 1111 VST4 (single 4-element structure from one lane) Offset 0 00 11 != 11x1 VST4 (single 4-element structure from one lane) Post-indexed 0 01 00 1101 VST1 (single element from one lane) Post-indexed 0 01 00 1111 VST1 (single element from one lane) Offset 0 01 00 != 11x1 VST1 (single element from one lane) Post-indexed 0 01 01 1101 VST2 (single 2-element structure from one lane) Post-indexed 0 01 01 1111 VST2 (single 2-element structure from one lane) Offset 0 01 01 != 11x1 VST2 (single 2-element structure from one lane) Post-indexed 0 01 10 1101 VST3 (single 3-element structure from one lane) Post-indexed 0 01 10 1111 VST3 (single 3-element structure from one lane) Offset 0 01 10 != 11x1 VST3 (single 3-element structure from one lane) Post-indexed 0 01 11 1101 VST4 (single 4-element structure from one lane) Post-indexed 0 01 11 1111 VST4 (single 4-element structure from one lane) Offset 0 01 11 != 11x1 VST4 (single 4-element structure from one lane) Post-indexed 0 10 00 1101 VST1 (single element from one lane) Post-indexed 0 10 00 1111 VST1 (single element from one lane) Offset 0 10 00 != 11x1 VST1 (single element from one lane) Post-indexed 0 10 01 1101 VST2 (single 2-element structure from one lane) Post-indexed 0 10 01 1111 VST2 (single 2-element structure from one lane) Offset 0 10 01 != 11x1 VST2 (single 2-element structure from one lane) Post-indexed 0 10 10 1101 VST3 (single 3-element structure from one lane) Post-indexed 0 10 10 1111 VST3 (single 3-element structure from one lane) Offset 0 10 10 != 11x1 VST3 (single 3-element structure from one lane) Post-indexed 0 10 11 1101 VST4 (single 4-element structure from one lane) Post-indexed 0 10 11 1111 VST4 (single 4-element structure from one lane) Offset 0 10 11 != 11x1 VST4 (single 4-element structure from one lane) Post-indexed 1 00 00 1101 VLD1 (single element to one lane) Post-indexed 1 00 00 1111 VLD1 (single element to one lane) Offset 1 00 00 != 11x1 VLD1 (single element to one lane) Post-indexed 1 00 01 1101 VLD2 (single 2-element structure to one lane) Post-indexed 1 00 01 1111 VLD2 (single 2-element structure to one lane) Offset 1 00 01 != 11x1 VLD2 (single 2-element structure to one lane) Post-indexed 1 00 10 1101 VLD3 (single 3-element structure to one lane) Post-indexed 1 00 10 1111 VLD3 (single 3-element structure to one lane) Offset 1 00 10 != 11x1 VLD3 (single 3-element structure to one lane) Post-indexed 1 00 11 1101 VLD4 (single 4-element structure to one lane) Post-indexed 1 00 11 1111 VLD4 (single 4-element structure to one lane) Offset 1 00 11 != 11x1 VLD4 (single 4-element structure to one lane) Post-indexed 1 01 00 1101 VLD1 (single element to one lane) Post-indexed 1 01 00 1111 VLD1 (single element to one lane) Offset 1 01 00 != 11x1 VLD1 (single element to one lane) Post-indexed 1 01 01 1101 VLD2 (single 2-element structure to one lane) Post-indexed 1 01 01 1111 VLD2 (single 2-element structure to one lane) Offset 1 01 01 != 11x1 VLD2 (single 2-element structure to one lane) Post-indexed 1 01 10 1101 VLD3 (single 3-element structure to one lane) Post-indexed 1 01 10 1111 VLD3 (single 3-element structure to one lane) Offset 1 01 10 != 11x1 VLD3 (single 3-element structure to one lane) Post-indexed 1 01 11 1101 VLD4 (single 4-element structure to one lane) Post-indexed 1 01 11 1111 VLD4 (single 4-element structure to one lane) Offset 1 01 11 != 11x1 VLD4 (single 4-element structure to one lane) Post-indexed 1 10 00 1101 VLD1 (single element to one lane) Post-indexed 1 10 00 1111 VLD1 (single element to one lane) Offset 1 10 00 != 11x1 VLD1 (single element to one lane) Post-indexed 1 10 01 1101 VLD2 (single 2-element structure to one lane) Post-indexed 1 10 01 1111 VLD2 (single 2-element structure to one lane) Offset 1 10 01 != 11x1 VLD2 (single 2-element structure to one lane) Post-indexed 1 10 10 1101 VLD3 (single 3-element structure to one lane) Post-indexed 1 10 10 1111 VLD3 (single 3-element structure to one lane) Offset 1 10 10 != 11x1 VLD3 (single 3-element structure to one lane) Post-indexed 1 10 11 1101 VLD4 (single 4-element structure to one lane) Post-indexed 1 10 11 1111 VLD4 (single 4-element structure to one lane) Offset 1 10 11 != 11x1 VLD4 (single 4-element structure to one lane) Post-indexed 1 1 1 1 0 1 0 1 0 1 1 1 (1) (1) (1) (1) (1) (1) (1) (1) (0) (0) (0) (0) Decode fields Instruction page Encoding opcode option 0000 UNPREDICTABLE 0001 CLREX A1 001x UNPREDICTABLE 0100 0000 SSBB A1 0100 0100 PSSBB A1 0100 != 0x00 DSB A1 0101 DMB A1 0110 ISB A1 0111 SB A1 1xxx UNPREDICTABLE 1 1 1 1 0 1 0 0 1 (1) (1) (1) (1) Decode fields Instruction page Encoding D R Rn 0 0 Reserved hint, behaves as NOP 0 1 PLI (immediate, literal) A1 1 1111 PLD (literal) A1 1 0 != 1111 PLD, PLDW (immediate) Preload write 1 1 != 1111 PLD, PLDW (immediate) Preload read 1 1 1 1 0 1 1 0 1 (1) (1) (1) (1) 0 Decode fields Instruction page Encoding D o2 imm5:stype 0 0 Reserved hint, behaves as NOP 0 1 0000011 PLI (register) Rotate right with extend 0 1 != 0000011 PLI (register) Shift or rotate by value 1 0 0000011 PLD, PLDW (register) Preload write, rotate right with extend 1 0 != 0000011 PLD, PLDW (register) Preload write, optional shift or rotate 1 1 0000011 PLD, PLDW (register) Preload read, rotate right with extend 1 1 != 0000011 PLD, PLDW (register) Preload read, optional shift or rotate 1 1 1 1 0 0 0 1 0 0 0 0 (0) (0) (0) (0) (0) (0) 0 Decode fields Instruction page Encoding imod M op I F mode 1 0 0 0xxxx SETEND A1 1 0 0 1xxxx UNALLOCATED 1 0 1 UNALLOCATED 1 1 UNALLOCATED 00 0 0 UNALLOCATED 00 1 0 CPS, CPSID, CPSIE Change mode 01 0 UNALLOCATED 10 0 0 CPS, CPSID, CPSIE Interrupt enable 10 1 0 CPS, CPSID, CPSIE Interrupt enable and change mode 11 0 0 CPS, CPSID, CPSIE Interrupt disable 11 1 0 CPS, CPSID, CPSIE Interrupt disable and change mode 1 1 1 1 0 0 0 1 0 0 0 1 (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) 0 0 0 0 (0) (0) (0) (0) Instruction page Encoding SETPAN A1