ADR Form PC-relative address Form PC-relative address adds an immediate value to the PC value to form a PC-relative address, and writes the result to the destination register. For more information about the CONSTRAINED UNPREDICTABLE behavior, see Architectural Constraints on UNPREDICTABLE behaviors. The instruction aliases permit the addition or subtraction of the offset and the immediate offset to be specified separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more information, see Use of labels in UAL instruction syntax. This instruction is used by the aliases ADD (immediate, to PC) Never SUB (immediate, from PC) imm12 == '000000000000' i :: imm3 :: imm8 == '000000000000' See below for details of when each alias is preferred. It has encodings from the following instruction sets: A32 ( A1 and A2 ) and T32 ( T1 , T2 and T3 ) . != 1111 0 0 1 0 1 0 0 0 1 1 1 1 ADR{<c>}{<q>} <Rd>, <label> let d : integer = UInt(Rd); let imm32 : bits(32) = A32ExpandImm(imm12); let add : boolean = TRUE; != 1111 0 0 1 0 0 1 0 0 1 1 1 1 ADR{<c>}{<q>} <Rd>, <label> let d : integer = UInt(Rd); let imm32 : bits(32) = A32ExpandImm(imm12); let add : boolean = FALSE; 1 0 1 0 0 ADR{<c>}{<q>} <Rd>, <label> let d : integer = UInt(Rd); let imm32 : bits(32) = ZeroExtend{}(imm8::'00'); let add : boolean = TRUE; 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 0 ADR{<c>}{<q>} <Rd>, <label> let d : integer = UInt(Rd); let imm32 : bits(32) = ZeroExtend{}(i::imm3::imm8); let add : boolean = FALSE; // Armv8-A removes UNPREDICTABLE for R13 if d == 15 then UnpredictableProcedure(); end; 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 0 ADR{<c>}{<q>} <Rd>, <label> ADR{<c>}.W <Rd>, <label> let d : integer = UInt(Rd); let imm32 : bits(32) = ZeroExtend{}(i::imm3::imm8); let add : boolean = TRUE; // Armv8-A removes UNPREDICTABLE for R13 if d == 15 then UnpredictableProcedure(); end; <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rd> For the "A1" and "A2" variants: is the general-purpose destination register, encoded in the "Rd" field. If the PC is used, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC. <Rd> For the "T1", "T2", and "T3" variants: is the general-purpose destination register, encoded in the "Rd" field. <label> For the "A1" and "A2" variants: the label of an instruction or literal data item whose address is to be loaded into <Rd>. The assembler calculates the required value of the offset from the Align(PC, 4) value of the ADR instruction to this label. If the offset is zero or positive, encoding A1 is used, with imm32 equal to the offset. If the offset is negative, encoding A2 is used, with imm32 equal to the size of the offset. That is, the use of encoding A2 indicates that the required offset is minus the value of imm32. Permitted values of the size of the offset are any of the constants described in Modified immediate constants in A32 instructions. <label> For the "T1" variant: the label of an instruction or literal data item whose address is to be loaded into <Rd>. The assembler calculates the required value of the offset from the Align(PC, 4) value of the ADR instruction to this label. Permitted values of the size of the offset are multiples of 4 in the range 0 to 1020. <label> For the "T2" and "T3" variants: the label of an instruction or literal data item whose address is to be loaded into <Rd>. The assembler calculates the required value of the offset from the Align(PC, 4) value of the ADR instruction to this label. If the offset is zero or positive, encoding T3 is used, with imm32 equal to the offset. If the offset is negative, encoding T2 is used, with imm32 equal to the size of the offset. That is, the use of encoding T2 indicates that the required offset is minus the value of imm32. Permitted values of the size of the offset are 0-4095. Alias Conditions if ConditionPassed() then EncodingSpecificOperations(); let result : bits(32) = (if add then (AlignDownSize(PC32(),4) + imm32) else (AlignDownSize(PC32(),4) - imm32)); if d == 15 then // Can only occur for A32 encodings ALUWritePC(result); else R(d) = result; end; end; 2026-03-12 12:23:09 2025-09_rel_asl1