B Branch Branch causes a branch to a target address. For more information about the CONSTRAINED UNPREDICTABLE behavior, see Architectural Constraints on UNPREDICTABLE behaviors. Related encodings: Branches and miscellaneous control. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 , T2 , T3 and T4 ) . != 1111 1 0 1 0 B{<c>}{<q>} <label> let imm32 : bits(32) = SignExtend{}(imm24::'00'); 1 1 0 1 != 111x B<c>{<q>} <label> if cond == '1110' then See("UDF"); end; if cond == '1111' then See("SVC"); end; let imm32 : bits(32) = SignExtend{}(imm8::'0'); if InITBlock() then UnpredictableProcedure(); end; 1 1 1 0 0 B{<c>}{<q>} <label> let imm32 : bits(32) = SignExtend{}(imm11::'0'); if InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end; 1 1 1 1 0 != 111x 1 0 0 B<c>.W <label> B<c>{<q>} <label> if cond[3:1] == '111' then See("Related encodings"); end; let imm32 : bits(32) = SignExtend{}(S::J2::J1::imm6::imm11::'0'); if InITBlock() then UnpredictableProcedure(); end; 1 1 1 1 0 1 0 1 B{<c>}{<q>} <label> B{<c>}.W <label> let I1 : bit = NOT(J1 XOR S); let I2 : bit = NOT(J2 XOR S); let imm32 : bits(32) = SignExtend{}(S::I1::I2::imm10::imm11::'0'); if InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end; <c> For the "A1" variant: see Standard assembler syntax fields. <c> For the "T1" and "T3" variants: see Standard assembler syntax fields. Must not be AL or omitted. <c> For the "T2" and "T4" variants: see Standard assembler syntax fields. <q> See Standard assembler syntax fields. <label> For the "A1" variant: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the B instruction to this label, then selects an encoding that sets imm32 to that offset. Permitted offsets are multiples of 4 in the range –33554432 to 33554428. <label> For the "T1" variant: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the B instruction to this label, then selects an encoding that sets imm32 to that offset. Permitted offsets are even numbers in the range –256 to 254. <label> For the "T2" variant: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the B instruction to this label, then selects an encoding that sets imm32 to that offset. Permitted offsets are even numbers in the range –2048 to 2046. <label> For the "T3" variant: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the B instruction to this label, then selects an encoding that sets imm32 to that offset. Permitted offsets are even numbers in the range –1048576 to 1048574. <label> For the "T4" variant: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the B instruction to this label, then selects an encoding that sets imm32 to that offset. Permitted offsets are even numbers in the range –16777216 to 16777214. if ConditionPassed() then EncodingSpecificOperations(); BranchWritePC(PC32() + imm32, BranchType_DIR); end; 2026-03-12 12:23:09 2025-09_rel_asl1