BFI Bit Field Insert Bit Field Insert copies any number of low order bits from a register into the same number of adjacent bits at any position in the destination register. For more information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors. This instruction is a data-independent-time instruction as described in About the DIT bit. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 0 1 1 1 1 1 0 0 0 1 != 1111 BFI{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width> if Rn == '1111' then See("BFC"); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let msbit : integer{} = UInt(msb); let lsbit : integer{} = UInt(lsb); if d == 15 then UnpredictableProcedure(); end; if msbit < lsbit then UnpredictableProcedure(); end; msbit < lsbit 1 1 1 1 0 (0) 1 1 0 1 1 0 != 1111 0 (0) BFI{<c>}{<q>} <Rd>, <Rn>, #<lsb>, #<width> if Rn == '1111' then See("BFC"); end; let d : integer = UInt(Rd); let n : integer = UInt(Rn); let msbit : integer{} = UInt(msb); let lsbit : integer{} = UInt(imm3::imm2); // Armv8-A removes UNPREDICTABLE for R13 if d == 15 then UnpredictableProcedure(); end; if msbit < lsbit then UnpredictableProcedure(); end; msbit < lsbit <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rd> Is the general-purpose destination register, encoded in the "Rd" field. <Rn> Is the general-purpose source register, encoded in the "Rn" field. <lsb> For the "A1" variant: is the least significant destination bit, in the range 0 to 31, encoded in the "lsb" field. <lsb> For the "T1" variant: is the least significant destination bit, in the range 0 to 31, encoded in the "imm3:imm2" field. <width> Is the number of bits to be copied, in the range 1 to 32-<lsb>, encoded in the "msb" field as <lsb>+<width>-1. if ConditionPassed() then EncodingSpecificOperations(); R(d)[msbit:lsbit] = R(n)[(msbit-lsbit):0]; // Other bits of R[d] are unchanged end; 2026-03-12 12:23:09 2025-09_rel_asl1