BIC, BICS (register)
Bitwise Bit Clear (register)
Bitwise Bit Clear (register) performs a bitwise AND of a register
value and the complement of an optionally-shifted register value,
and writes the result to the destination register.
If the destination register is not the PC, the BICS variant of the
instruction updates the condition flags based on the result.
The field descriptions for <Rd> identify the encodings
where the PC is permitted as the destination register. Arm
deprecates any use of these encodings. However, when the destination
register is the PC:
The BIC variant of the instruction is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
The BICS variant of the instruction performs an exception return without the use of the stack. In this case:
The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.
The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32 state.
The instruction is UNDEFINED in Hyp mode.
The instruction is CONSTRAINED UNPREDICTABLE in User mode and System mode.
For more information about the CONSTRAINED UNPREDICTABLE behavior, see Architectural Constraints on UNPREDICTABLE behaviors.
This instruction is a data-independent-time instruction as described in About the DIT bit.
It has encodings from the following instruction sets:
A32 (
A1
)
and
T32 (
T1
and
T2
)
.
!= 1111
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
BIC{<c>}{<q>} {<Rd>, }<Rn>, <Rm>, RRX
0
BIC{<c>}{<q>} {<Rd>, }<Rn>, <Rm> {, <shift> #<amount>}
1
0
0
0
0
0
1
1
BICS{<c>}{<q>} {<Rd>, }<Rn>, <Rm>, RRX
1
BICS{<c>}{<q>} {<Rd>, }<Rn>, <Rm> {, <shift> #<amount>}
let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let setflags : boolean = (S == '1');
let (shift_t, shift_n) : (SRType, integer) = DecodeImmShift(stype, imm5);
0
1
0
0
0
0
1
1
1
0
BIC<c>{<q>} {<Rdn>, }<Rdn>, <Rm>
BICS{<q>} {<Rdn>, }<Rdn>, <Rm>
let d : integer = UInt(Rdn);
let n : integer = UInt(Rdn);
let m : integer = UInt(Rm);
let setflags : boolean = !InITBlock();
let shift_t : SRType = SRType_LSL;
let shift_n : integer = 0;
1
1
1
0
1
0
1
0
0
0
1
(0)
0
0
0
0
0
0
1
1
BIC{<c>}{<q>} {<Rd>, }<Rn>, <Rm>, RRX
0
BIC{<c>}{<q>} {<Rd>, }<Rn>, <Rm> {, <shift> #<amount>}
BIC<c>.W {<Rd>, }<Rn>, <Rm>
1
0
0
0
0
0
1
1
BICS{<c>}{<q>} {<Rd>, }<Rn>, <Rm>, RRX
1
BICS{<c>}{<q>} {<Rd>, }<Rn>, <Rm> {, <shift> #<amount>}
BICS.W {<Rd>, }<Rn>, <Rm>
let d : integer = UInt(Rd);
let n : integer = UInt(Rn);
let m : integer = UInt(Rm);
let setflags : boolean = (S == '1');
let (shift_t, shift_n) : (SRType, integer) = DecodeImmShift(stype, imm3::imm2);
// Armv8-A removes UNPREDICTABLE for R13
if d == 15 || n == 15 || m == 15 then UnpredictableProcedure(); end;
<c>
See Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<Rd>
For the "A1 BIC, rotate right with extend", "A1 BIC, shift or rotate by value", "A1 BICS, rotate right with extend", and "A1 BICS, shift or rotate by value" variants: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <Rn>. Arm deprecates using the PC as the destination register, but if the PC is used:
For the BIC variant, the instruction is a branch to the address calculated by the operation. This is an interworking branch, see Pseudocode description of operations on the AArch32 general-purpose registers and the PC.
For the BICS variant, the instruction performs an exception return, that restores PSTATE from SPSR_<current_mode>.
<Rd>
For the "T2 BIC, rotate right with extend", "T2 BIC, shift or rotate by value", "T2 BICS, rotate right with extend", and "T2 BICS, shift or rotate by value" variants: is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the same as <Rn>.
<Rn>
For the "A1 BIC, rotate right with extend", "A1 BIC, shift or rotate by value", "A1 BICS, rotate right with extend", and "A1 BICS, shift or rotate by value" variants: is the first general-purpose source register, encoded in the "Rn" field. The PC can be used, but this is deprecated.
<Rn>
For the "T2 BIC, rotate right with extend", "T2 BIC, shift or rotate by value", "T2 BICS, rotate right with extend", and "T2 BICS, shift or rotate by value" variants: is the first general-purpose source register, encoded in the "Rn" field.
<Rm>
For the "A1 BIC, rotate right with extend", "A1 BIC, shift or rotate by value", "A1 BICS, rotate right with extend", and "A1 BICS, shift or rotate by value" variants: is the second general-purpose source register, encoded in the "Rm" field. The PC can be used, but this is deprecated.
<Rm>
For the "T1", "T2 BIC, rotate right with extend", "T2 BIC, shift or rotate by value", "T2 BICS, rotate right with extend", and "T2 BICS, shift or rotate by value" variants: is the second general-purpose source register, encoded in the "Rm" field.
<shift>
Is the type of shift to be applied to the second source register,
stype
<shift>
00
LSL
01
LSR
10
ASR
11
ROR
<amount>
For the "A1 BIC, shift or rotate by value" and "A1 BICS, shift or rotate by value" variants: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR), encoded in the "imm5" field as <amount> modulo 32.
<amount>
For the "T2 BIC, shift or rotate by value" and "T2 BICS, shift or rotate by value" variants: is the shift amount, in the range 1 to 31 (when <shift> = LSL or ROR) or 1 to 32 (when <shift> = LSR or ASR), encoded in the "imm3:imm2" field as <amount> modulo 32.
<Rdn>
Is the first general-purpose source register and the destination register, encoded in the "Rdn" field.
if ConditionPassed() then
EncodingSpecificOperations();
let (shifted, carry) : (bits(32), bit) = Shift_C{32}(R(m), shift_t, shift_n, PSTATE.C);
let result : bits(32) = R(n) AND NOT(shifted);
if d == 15 then // Can only occur for A32 encoding
if setflags then
ALUExceptionReturn(result);
else
ALUWritePC(result);
end;
else
R(d) = result;
if setflags then
PSTATE.N = result[31];
PSTATE.Z = IsZeroBit{32}(result);
PSTATE.C = carry;
// PSTATE.V unchanged
end;
end;
end;
2026-03-12 12:23:09
2025-09_rel_asl1