BL, BLX (immediate)
Branch with Link and optional Exchange (immediate)
Branch with Link calls a subroutine at a PC-relative address,
and setting LR to the return address.
Branch with Link and Exchange Instruction Sets (immediate)
calls a subroutine at a PC-relative address, setting LR to
the return address, and changes the instruction
set from A32 to T32, or from T32 to A32.
For more information about the CONSTRAINED UNPREDICTABLE behavior, see Architectural Constraints on UNPREDICTABLE behaviors.
It has encodings from the following instruction sets:
A32 (
A1
and
A2
)
and
T32 (
T1
and
T2
)
.
!= 1111
1
0
1
1
BL{<c>}{<q>} <label>
let imm32 : bits(32) = SignExtend{}(imm24::'00');
let targetInstrSet : InstrSet = InstrSet_A32;
1
1
1
1
1
0
1
BLX{<c>}{<q>} <label>
let imm32 : bits(32) = SignExtend{}(imm24::H::'0');
let targetInstrSet : InstrSet = InstrSet_T32;
1
1
1
1
0
1
1
1
BL{<c>}{<q>} <label>
let I1 : bit = NOT(J1 XOR S);
let I2 : bit = NOT(J2 XOR S);
let imm32 : bits(32) = SignExtend{}(S::I1::I2::imm10::imm11::'0');
let targetInstrSet : InstrSet = InstrSet_T32;
if InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end;
1
1
1
1
0
1
1
0
BLX{<c>}{<q>} <label>
if H == '1' then Undefined(); end;
let I1 : bit = NOT(J1 XOR S);
let I2 : bit = NOT(J2 XOR S);
let imm32 : bits(32) = SignExtend{}(S::I1::I2::imm10H::imm10L::'00');
let targetInstrSet : InstrSet = InstrSet_A32;
if InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end;
<c>
For the "A1" variant: see Standard assembler syntax fields.
<c>
For the "A2" variant: see Standard assembler syntax fields. <c> must be AL or omitted.
<c>
For the "T1" and "T2" variants: see Standard assembler syntax fields.
<q>
See Standard assembler syntax fields.
<label>
For the "A1" variant: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the BL instruction to this label, then selects an encoding that sets imm32 to that offset.
Permitted offsets are multiples of 4 in the range –33554432 to 33554428.
<label>
For the "A2" variant: the label of the instruction that is to be branched to. The assembler calculates the required value of the offset from the PC value of the BLX instruction to this label, then selects an encoding with imm32 set to that offset.
Permitted offsets are even numbers in the range –33554432 to 33554430.
<label>
For the "T1" variant: the label of the instruction that is to be branched to.
The assembler calculates the required value of the offset from the PC value of the BL instruction to this label, then selects an encoding with imm32 set to that offset.
Permitted offsets are even numbers in the range –16777216 to 16777214.
<label>
For the "T2" variant: the label of the instruction that is to be branched to.
The assembler calculates the required value of the offset from the Align(PC, 4) value of the BLX instruction to this label, then selects an encoding with imm32 set to that offset.
Permitted offsets are multiples of 4 in the range –16777216 to 16777212.
if ConditionPassed() then
EncodingSpecificOperations();
if CurrentInstrSet() == InstrSet_A32 then
LR() = PC32() - 4;
else
LR() = PC32()[31:1] :: '1';
end;
var targetAddress : bits(32);
if targetInstrSet == InstrSet_A32 then
targetAddress = AlignDownSize(PC32(),4) + imm32;
else
targetAddress = PC32() + imm32;
end;
SelectInstrSet(targetInstrSet);
BranchWritePC(targetAddress, BranchType_DIRCALL);
end;
2026-03-12 12:23:09
2025-09_rel_asl1