BLX (register) Branch with Link and Exchange (register) Branch with Link and Exchange (register) calls a subroutine at an address specified in the register, and if necessary changes to the instruction set indicated by bit[0] of the register value. If the value in bit[0] is 0, the instruction set after the branch will be A32. If the value in bit[0] is 1, the instruction set after the branch will be T32. For more information about the CONSTRAINED UNPREDICTABLE behavior, see Architectural Constraints on UNPREDICTABLE behaviors. It has encodings from the following instruction sets: A32 ( A1 ) and T32 ( T1 ) . != 1111 0 0 0 1 0 0 1 0 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 0 0 1 1 BLX{<c>}{<q>} <Rm> let m : integer = UInt(Rm); if m == 15 then UnpredictableProcedure(); end; 0 1 0 0 0 1 1 1 1 (0) (0) (0) BLX{<c>}{<q>} <Rm> let m : integer = UInt(Rm); if m == 15 then UnpredictableProcedure(); end; if InITBlock() && !LastInITBlock() then UnpredictableProcedure(); end; <c> See Standard assembler syntax fields. <q> See Standard assembler syntax fields. <Rm> Is the general-purpose register holding the address to be branched to, encoded in the "Rm" field. if ConditionPassed() then EncodingSpecificOperations(); let target : bits(32) = R(m); var next_instr_addr : bits(32); if CurrentInstrSet() == InstrSet_A32 then next_instr_addr = PC32() - 4; LR() = next_instr_addr; else next_instr_addr = PC32() - 2; LR() = next_instr_addr[31:1] :: '1'; end; BXWritePC(target, BranchType_INDCALL); end; 2026-03-12 12:23:09 2025-09_rel_asl1